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This is the bulk of pin control changes for the v3.18 

development series:
 
 - New drivers for the Freescale i.MX21, Qualcomm APQ8084
   pin controllers.
 
 - Incremental new features on the Rockchip, atlas 6,
   OMAP, AM437x, APQ8064, prima2, AT91, Tegra, i.MX, Berlin
   and Nomadik.
 
 - Push Freescale drivers down into their own subdirectory.
 
 - Assorted sprays of syntax and semantic fixes.
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Merge tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control changes from Linus Walleij:
 "This is the bulk of pin control changes for the v3.18 development
  series:

   - New drivers for the Freescale i.MX21, Qualcomm APQ8084 pin
     controllers.

   - Incremental new features on the Rockchip, atlas 6, OMAP, AM437x,
     APQ8064, prima2, AT91, Tegra, i.MX, Berlin and Nomadik.

   - Push Freescale drivers down into their own subdirectory.

   - Assorted sprays of syntax and semantic fixes"

* tag 'pinctrl-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (48 commits)
  pinctrl: specify bindings for pins and groups
  pinctrl: nomadik: improve GPIO debug prints
  pinctrl: abx500: refactor DT parser to take two paths
  pinctrl: abx500: use helpers for map allocation/free
  pinctrl: alter device tree bindings for functions
  pinctrl: nomadik: refactor DT parser to take two paths
  pinctrl: nomadik: use utils map free function
  pinctrl: nomadik: use util function to reserve maps
  pinctrl: qcom: use restart_notifier mechanism for ps_hold
  pinctrl: sh-pfc: sh73a0: Remove unnecessary SoC data allocation
  pinctrl: berlin: fix the dt_free_map function
  pinctrl: at91: disable PD or PU before enabling PU or PD
  pinctrl: st: remove gpiochip in failure cases
  pinctrl: at91: Fix error handling while doing gpiochio_irqchip_add
  pinctrl: at91: Fix failure path in at91_gpio_probe path
  pinctrl: lantiq: Release gpiochip resources in fail case
  pinctrl: imx: detect uninitialized pins
  pinctrl: tegra: Add MIPI pad control
  pinctrl: at91: Switch to using managed clk_get
  pinctrl: adi2: Remove duplicate gpiochip_remove_pin_ranges
  ...
wifi-calibration
Linus Torvalds 2014-10-07 20:56:28 -04:00
parent c91662cb18 2cdef8f4e1
commit 2b425a3f11
94 changed files with 2839 additions and 613 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
Documentation/devicetree/bindings/pinctrl/atmel,at91-pinctrl.txt
View File

@ -19,6 +19,7 @@ such as pull-up, multi drive, etc.
Required properties for iomux controller:
- compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
or "atmel,sama5d3-pinctrl"
- atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
configured in this periph mode. All the periph and bank need to be describe.
@ -85,13 +86,20 @@ Required properties for pin configuration node:
PIN_BANK 0 is pioA, PIN_BANK 1 is pioB...
Bits used for CONFIG:
PULL_UP (1 << 0): indicate this pin need a pull up.
MULTIDRIVE (1 << 1): indicate this pin need to be configured as multidrive.
DEGLITCH (1 << 2): indicate this pin need deglitch.
PULL_DOWN (1 << 3): indicate this pin need a pull down.
DIS_SCHMIT (1 << 4): indicate this pin need to disable schmit trigger.
DEBOUNCE (1 << 16): indicate this pin need debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce val.
PULL_UP (1 << 0): indicate this pin needs a pull up.
MULTIDRIVE (1 << 1): indicate this pin needs to be configured as multi-drive.
Multi-drive is equivalent to open-drain type output.
DEGLITCH (1 << 2): indicate this pin needs deglitch.
PULL_DOWN (1 << 3): indicate this pin needs a pull down.
DIS_SCHMIT (1 << 4): indicate this pin needs to the disable schmitt trigger.
DRIVE_STRENGTH (3 << 5): indicate the drive strength of the pin using the
following values:
00 - No change (reset state value kept)
01 - Low
10 - Medium
11 - High
DEBOUNCE (1 << 16): indicate this pin needs debounce.
DEBOUNCE_VAL (0x3fff << 17): debounce value.
NOTE:
Some requirements for using atmel,at91rm9200-pinctrl binding:

14
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
View File

@ -10,6 +10,7 @@ Required properties:
- reg: Should contain a list of base address and size pairs for:
-- first entry - the drive strength and pad control registers.
-- second entry - the pinmux registers
-- third entry - the MIPI_PAD_CTRL register
Tegra124 adds the following optional properties for pin configuration subnodes.
The macros for options are defined in the
@ -91,6 +92,12 @@ Valid values for pin and group names are:
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
MIPI pad control groups:
These support only the nvidia,function property.
dsi_b
Valid values for nvidia,functions are:
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
@ -101,14 +108,15 @@ Valid values for nvidia,functions are:
sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
dp, rtck, sys, clk tmds.
dp, rtck, sys, clk tmds, csi, dsi_b
Example:
pinmux: pinmux {
compatible = "nvidia,tegra124-pinmux";
reg = <0x70000868 0x164 /* Pad control registers */
0x70003000 0x434>; /* PinMux registers */
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
<0x0 0x70003000 0x0 0x434>, /* Mux registers */
<0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
};
Example pinmux entries:

50
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
View File

@ -127,6 +127,24 @@ whether there is any interaction between the child and intermediate parent
nodes, is again defined entirely by the binding for the individual pin
controller device.
== Generic pin multiplexing node content ==
pin multiplexing nodes:
function - the mux function to select
groups - the list of groups to select with this function
Example:
state_0_node_a {
function = "uart0";
groups = "u0rxtx", "u0rtscts";
};
state_1_node_a {
function = "spi0";
groups = "spi0pins";
};
== Generic pin configuration node content ==
Many data items that are represented in a pin configuration node are common
@ -139,8 +157,12 @@ structure of the DT nodes that contain these properties.
Supported generic properties are:
pins - the list of pins that properties in the node
apply to
function - the mux function to select
apply to (either this or "group" has to be
specified)
group - the group to apply the properties to, if the driver
supports configuration of whole groups rather than
individual pins (either this or "pins" has to be
specified)
bias-disable - disable any pin bias
bias-high-impedance - high impedance mode ("third-state", "floating")
bias-bus-hold - latch weakly
@ -163,6 +185,21 @@ output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
slew-rate - set the slew rate
For example:
state_0_node_a {
pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
bias-pull-up;
};
state_1_node_a {
pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
output-high;
};
state_2_node_a {
group = "foo-group";
bias-pull-up;
};
Some of the generic properties take arguments. For those that do, the
arguments are described below.
@ -170,15 +207,6 @@ arguments are described below.
binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- function takes a list of function names/IDs as a required argument. The
specific binding for the hardware defines:
- Whether the entries are integers or strings, and their meaning.
- Whether only a single entry is allowed (which is applied to all entries
in the pins property), or whether there may alternatively be one entry per
entry in the pins property, in which case the list lengths must match, and
for each list index i, the function at list index i is applied to the pin
at list index i.
- bias-pull-up, -down and -pin-default take as optional argument on hardware
supporting it the pull strength in Ohm. bias-disable will disable the pull.

2
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
View File

@ -50,7 +50,7 @@ Valid values for function are:
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,
riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic,
riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold
Example:

179
Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.txt 100644
View File

@ -0,0 +1,179 @@
Qualcomm APQ8084 TLMM block
This binding describes the Top Level Mode Multiplexer block found in the
MSM8960 platform.
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,apq8084-pinctrl"
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: the base address and size of the TLMM register space.
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the TLMM summary IRQ.
- interrupt-controller:
Usage: required
Value type: <none>
Definition: identifies this node as an interrupt controller
- #interrupt-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/interrupt-controller/irq.h>
- gpio-controller:
Usage: required
Value type: <none>
Definition: identifies this node as a gpio controller
- #gpio-cells:
Usage: required
Value type: <u32>
Definition: must be 2. Specifying the pin number and flags, as defined
in <dt-bindings/gpio/gpio.h>
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
a general description of GPIO and interrupt bindings.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".
The pin configuration nodes act as a container for an abitrary number of
subnodes. Each of these subnodes represents some desired configuration for a
pin, a group, or a list of pins or groups. This configuration can include the
mux function to select on those pin(s)/group(s), and various pin configuration
parameters, such as pull-up, drive strength, etc.
PIN CONFIGURATION NODES:
The name of each subnode is not important; all subnodes should be enumerated
and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function.
The following generic properties as defined in pinctrl-bindings.txt are valid
to specify in a pin configuration subnode:
- pins:
Usage: required
Value type: <string-array>
Definition: List of gpio pins affected by the properties specified in
this subnode. Valid pins are:
gpio0-gpio146,
sdc1_clk,
sdc1_cmd,
sdc1_data
sdc2_clk,
sdc2_cmd,
sdc2_data
- function:
Usage: required
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Functions are only valid for gpio pins.
Valid values are:
adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3,
blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8,
blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12,
blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5,
blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10,
blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3,
blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8,
blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12,
blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10,
blsp_uim11, blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2,
cam_mclk3, cci_async, cci_async_in0, cci_i2c0, cci_i2c1,
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, gcc_obt, gcc_vtt,i
gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, gp1_clk, gpio,
hdmi_cec, hdmi_ddc, hdmi_dtest, hdmi_hpd, hdmi_rcv, hsic,
ldo_en, ldo_update, mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst,
pci_e1, pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s,
qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n,
sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus,
spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, tsif1,
tsif2, uim, uim_batt_alarm
- bias-disable:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as no pull.
- bias-pull-down:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull down.
- bias-pull-up:
Usage: optional
Value type: <none>
Definition: The specified pins should be configued as pull up.
- output-high:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
high.
Not valid for sdc pins.
- output-low:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in output mode, driven
low.
Not valid for sdc pins.
- drive-strength:
Usage: optional
Value type: <u32>
Definition: Selects the drive strength for the specified pins, in mA.
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
Example:
tlmm: pinctrl@fd510000 {
compatible = "qcom,apq8084-pinctrl";
reg = <0xfd510000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <0 208 0>;
uart2: uart2-default {
mux {
pins = "gpio4", "gpio5";
function = "blsp_uart2";
};
tx {
pins = "gpio4";
drive-strength = <4>;
bias-disable;
};
rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
};
};

6
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View File

@ -2,8 +2,8 @@
The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to
4 muxing options with option 0 being the use as a GPIO.
multiplexing the PAD input/output signals. For each PAD there are several
muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
The MUX 0 means gpio and MUX 1 to 3 mean the specific device function.
The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory.

13
Documentation/devicetree/bindings/pinctrl/ti,omap-pinctrl.txt 100644
View File

@ -0,0 +1,13 @@
OMAP Pinctrl definitions
Required properties:
- compatible : Should be one of:
"ti,omap2420-padconf" - OMAP2420 compatible pinctrl
"ti,omap2430-padconf" - OMAP2430 compatible pinctrl
"ti,omap3-padconf" - OMAP3 compatible pinctrl
"ti,omap4-padconf" - OMAP4 compatible pinctrl
"ti,omap5-padconf" - OMAP5 compatible pinctrl
"ti,dra7-padconf" - DRA7 compatible pinctrl
"ti,am437-padconf" - AM437x compatible pinctrl
See Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt for further details.

14
Documentation/pinctrl.txt
View File

@ -702,7 +702,7 @@ static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
u8 regbit = (1 << selector + group);
@ -711,21 +711,11 @@ int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
u8 regbit = (1 << selector + group);
writeb((readb(MUX) & ~(regbit)), MUX)
return 0;
}
struct pinmux_ops foo_pmxops = {
.get_functions_count = foo_get_functions_count,
.get_function_name = foo_get_fname,
.get_function_groups = foo_get_groups,
.enable = foo_enable,
.disable = foo_disable,
.set_mux = foo_set_mux,
};
/* Pinmux operations are handled by some pin controller */

6
arch/arm/mach-at91/include/mach/at91_pio.h
View File

@ -71,4 +71,10 @@
#define ABCDSR_PERIPH_C 0x2
#define ABCDSR_PERIPH_D 0x3
#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
#endif

103
drivers/pinctrl/Kconfig
View File

@ -97,95 +97,6 @@ config PINCTRL_BCM281XX
BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
framework. GPIO is provided by a separate GPIO driver.
config PINCTRL_IMX
bool
select PINMUX
select PINCONF
config PINCTRL_IMX1_CORE
bool
select PINMUX
select PINCONF
config PINCTRL_IMX1
bool "IMX1 pinctrl driver"
depends on SOC_IMX1
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx1 pinctrl driver
config PINCTRL_IMX27
bool "IMX27 pinctrl driver"
depends on SOC_IMX27
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx27 pinctrl driver
config PINCTRL_IMX25
bool "IMX25 pinctrl driver"
depends on OF
depends on SOC_IMX25
select PINCTRL_IMX
help
Say Y here to enable the imx25 pinctrl driver
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on SOC_IMX35
select PINCTRL_IMX
help
Say Y here to enable the imx35 pinctrl driver
config PINCTRL_IMX50
bool "IMX50 pinctrl driver"
depends on SOC_IMX50
select PINCTRL_IMX
help
Say Y here to enable the imx50 pinctrl driver
config PINCTRL_IMX51
bool "IMX51 pinctrl driver"
depends on SOC_IMX51
select PINCTRL_IMX
help
Say Y here to enable the imx51 pinctrl driver
config PINCTRL_IMX53
bool "IMX53 pinctrl driver"
depends on SOC_IMX53
select PINCTRL_IMX
help
Say Y here to enable the imx53 pinctrl driver
config PINCTRL_IMX6Q
bool "IMX6Q/DL pinctrl driver"
depends on SOC_IMX6Q
select PINCTRL_IMX
help
Say Y here to enable the imx6q/dl pinctrl driver
config PINCTRL_IMX6SL
bool "IMX6SL pinctrl driver"
depends on SOC_IMX6SL
select PINCTRL_IMX
help
Say Y here to enable the imx6sl pinctrl driver
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
depends on SOC_IMX6SX
select PINCTRL_IMX
help
Say Y here to enable the imx6sx pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
select PINCTRL_IMX
help
Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
config PINCTRL_LANTIQ
bool
depends on LANTIQ
@ -197,19 +108,6 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
config PINCTRL_MXS
bool
select PINMUX
select PINCONF
config PINCTRL_IMX23
bool
select PINCTRL_MXS
config PINCTRL_IMX28
bool
select PINCTRL_MXS
config PINCTRL_ROCKCHIP
bool
select PINMUX
@ -306,6 +204,7 @@ config PINCTRL_PALMAS
TPS65913, TPS80036 etc.
source "drivers/pinctrl/berlin/Kconfig"
source "drivers/pinctrl/freescale/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/nomadik/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"

23
drivers/pinctrl/Makefile
View File

@ -17,23 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
@ -52,15 +36,14 @@ obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-y += freescale/
obj-$(CONFIG_PLAT_ORION) += mvebu/
obj-y += nomadik/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
obj-$(CONFIG_SUPERH) += sh-pfc/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_VT8500) += vt8500/

29
drivers/pinctrl/berlin/berlin.c
View File

@ -99,30 +99,11 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev,
return 0;
}
static void berlin_pinctrl_dt_free_map(struct pinctrl_dev *pctrl_dev,
struct pinctrl_map *map,
unsigned nmaps)
{
int i;
for (i = 0; i < nmaps; i++) {
if (map[i].type == PIN_MAP_TYPE_MUX_GROUP) {
kfree(map[i].data.mux.group);
/* a function can be applied to multiple groups */
if (i == 0)
kfree(map[i].data.mux.function);
}
}
kfree(map);
}
static const struct pinctrl_ops berlin_pinctrl_ops = {
.get_groups_count = &berlin_pinctrl_get_group_count,
.get_group_name = &berlin_pinctrl_get_group_name,
.dt_node_to_map = &berlin_pinctrl_dt_node_to_map,
.dt_free_map = &berlin_pinctrl_dt_free_map,
.dt_free_map = &pinctrl_utils_dt_free_map,
};
static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev)
@ -170,9 +151,9 @@ berlin_pinctrl_find_function_by_name(struct berlin_pinctrl *pctrl,
return NULL;
}
static int berlin_pinmux_enable(struct pinctrl_dev *pctrl_dev,
unsigned function,
unsigned group)
static int berlin_pinmux_set(struct pinctrl_dev *pctrl_dev,
unsigned function,
unsigned group)
{
struct berlin_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
const struct berlin_desc_group *group_desc = pctrl->desc->groups + group;
@ -197,7 +178,7 @@ static const struct pinmux_ops berlin_pinmux_ops = {
.get_functions_count = &berlin_pinmux_get_functions_count,
.get_function_name = &berlin_pinmux_get_function_name,
.get_function_groups = &berlin_pinmux_get_function_groups,
.enable = &berlin_pinmux_enable,
.set_mux = &berlin_pinmux_set,
};
static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,

108
drivers/pinctrl/freescale/Kconfig 100644
View File

@ -0,0 +1,108 @@
config PINCTRL_IMX
bool
select PINMUX
select PINCONF
config PINCTRL_IMX1_CORE
bool
select PINMUX
select PINCONF
config PINCTRL_IMX1
bool "IMX1 pinctrl driver"
depends on SOC_IMX1
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx1 pinctrl driver
config PINCTRL_IMX21
bool "i.MX21 pinctrl driver"
depends on SOC_IMX21
select PINCTRL_IMX1_CORE
help
Say Y here to enable the i.MX21 pinctrl driver
config PINCTRL_IMX27
bool "IMX27 pinctrl driver"
depends on SOC_IMX27
select PINCTRL_IMX1_CORE
help
Say Y here to enable the imx27 pinctrl driver
config PINCTRL_IMX25
bool "IMX25 pinctrl driver"
depends on OF
depends on SOC_IMX25
select PINCTRL_IMX
help
Say Y here to enable the imx25 pinctrl driver
config PINCTRL_IMX35
bool "IMX35 pinctrl driver"
depends on SOC_IMX35
select PINCTRL_IMX
help
Say Y here to enable the imx35 pinctrl driver
config PINCTRL_IMX50
bool "IMX50 pinctrl driver"
depends on SOC_IMX50
select PINCTRL_IMX
help
Say Y here to enable the imx50 pinctrl driver
config PINCTRL_IMX51
bool "IMX51 pinctrl driver"
depends on SOC_IMX51
select PINCTRL_IMX
help
Say Y here to enable the imx51 pinctrl driver
config PINCTRL_IMX53
bool "IMX53 pinctrl driver"
depends on SOC_IMX53
select PINCTRL_IMX
help
Say Y here to enable the imx53 pinctrl driver
config PINCTRL_IMX6Q
bool "IMX6Q/DL pinctrl driver"
depends on SOC_IMX6Q
select PINCTRL_IMX
help
Say Y here to enable the imx6q/dl pinctrl driver
config PINCTRL_IMX6SL
bool "IMX6SL pinctrl driver"
depends on SOC_IMX6SL
select PINCTRL_IMX
help
Say Y here to enable the imx6sl pinctrl driver
config PINCTRL_IMX6SX
bool "IMX6SX pinctrl driver"
depends on SOC_IMX6SX
select PINCTRL_IMX
help
Say Y here to enable the imx6sx pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610
select PINCTRL_IMX
help
Say Y here to enable the Freescale Vybrid VF610 pinctrl driver
config PINCTRL_MXS
bool
select PINMUX
select PINCONF
config PINCTRL_IMX23
bool
select PINCTRL_MXS
config PINCTRL_IMX28
bool
select PINCTRL_MXS

19
drivers/pinctrl/freescale/Makefile 100644
View File

@ -0,0 +1,19 @@
# Freescale pin control drivers
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o
obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o
obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o

17
drivers/pinctrl/pinctrl-imx.c → drivers/pinctrl/freescale/pinctrl-imx.c
View File

@ -24,7 +24,7 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "../core.h"
#include "pinctrl-imx.h"
/* The bits in CONFIG cell defined in binding doc*/
@ -179,8 +179,8 @@ static const struct pinctrl_ops imx_pctrl_ops = {
};
static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx_pinctrl_soc_info *info = ipctl->info;
@ -204,7 +204,7 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
pin_id = pin->pin;
pin_reg = &info->pin_regs[pin_id];
if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
if (pin_reg->mux_reg == -1) {
dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
info->pins[pin_id].name);
return -EINVAL;
@ -298,7 +298,7 @@ static const struct pinmux_ops imx_pmx_ops = {
.get_functions_count = imx_pmx_get_funcs_count,
.get_function_name = imx_pmx_get_func_name,
.get_function_groups = imx_pmx_get_groups,
.enable = imx_pmx_enable,
.set_mux = imx_pmx_set,
};
static int imx_pinconf_get(struct pinctrl_dev *pctldev,
@ -308,7 +308,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
if (pin_reg->conf_reg == -1) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
@ -331,7 +331,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
int i;
if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
if (pin_reg->conf_reg == -1) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
@ -586,10 +586,11 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
info->pin_regs = devm_kzalloc(&pdev->dev, sizeof(*info->pin_regs) *
info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
info->npins, GFP_KERNEL);
if (!info->pin_regs)
return -ENOMEM;
memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ipctl->base = devm_ioremap_resource(&pdev->dev, res);

7
drivers/pinctrl/pinctrl-imx.h → drivers/pinctrl/freescale/pinctrl-imx.h
View File

@ -67,8 +67,8 @@ struct imx_pmx_func {
* @conf_reg: config register offset
*/
struct imx_pin_reg {
u16 mux_reg;
u16 conf_reg;
s16 mux_reg;
s16 conf_reg;
};
struct imx_pinctrl_soc_info {
@ -83,8 +83,7 @@ struct imx_pinctrl_soc_info {
unsigned int flags;
};
#define ZERO_OFFSET_VALID 0x1
#define SHARE_MUX_CONF_REG 0x2
#define SHARE_MUX_CONF_REG 0x1
#define NO_MUX 0x0
#define NO_PAD 0x0

8
drivers/pinctrl/pinctrl-imx1-core.c → drivers/pinctrl/freescale/pinctrl-imx1-core.c
View File

@ -28,7 +28,7 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include "core.h"
#include "../core.h"
#include "pinctrl-imx1.h"
struct imx1_pinctrl {
@ -298,8 +298,8 @@ static const struct pinctrl_ops imx1_pctrl_ops = {
};
static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int imx1_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
const struct imx1_pinctrl_soc_info *info = ipctl->info;
@ -385,7 +385,7 @@ static const struct pinmux_ops imx1_pmx_ops = {
.get_functions_count = imx1_pmx_get_funcs_count,
.get_function_name = imx1_pmx_get_func_name,
.get_function_groups = imx1_pmx_get_groups,
.enable = imx1_pmx_enable,
.set_mux = imx1_pmx_set,
};
static int imx1_pinconf_get(struct pinctrl_dev *pctldev,

0
drivers/pinctrl/pinctrl-imx1.c → drivers/pinctrl/freescale/pinctrl-imx1.c
View File

0
drivers/pinctrl/pinctrl-imx1.h → drivers/pinctrl/freescale/pinctrl-imx1.h
View File

342
drivers/pinctrl/freescale/pinctrl-imx21.c 100644
View File

@ -0,0 +1,342 @@
/*
* i.MX21 pinctrl driver based on imx pinmux core
*
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx1.h"
#define PAD_ID(port, pin) ((port) * 32 + (pin))
#define PA 0
#define PB 1
#define PC 2
#define PD 3
#define PE 4
#define PF 5
enum imx21_pads {
MX21_PAD_LSCLK = PAD_ID(PA, 5),
MX21_PAD_LD0 = PAD_ID(PA, 6),
MX21_PAD_LD1 = PAD_ID(PA, 7),
MX21_PAD_LD2 = PAD_ID(PA, 8),
MX21_PAD_LD3 = PAD_ID(PA, 9),
MX21_PAD_LD4 = PAD_ID(PA, 10),
MX21_PAD_LD5 = PAD_ID(PA, 11),
MX21_PAD_LD6 = PAD_ID(PA, 12),
MX21_PAD_LD7 = PAD_ID(PA, 13),
MX21_PAD_LD8 = PAD_ID(PA, 14),
MX21_PAD_LD9 = PAD_ID(PA, 15),
MX21_PAD_LD10 = PAD_ID(PA, 16),
MX21_PAD_LD11 = PAD_ID(PA, 17),
MX21_PAD_LD12 = PAD_ID(PA, 18),
MX21_PAD_LD13 = PAD_ID(PA, 19),
MX21_PAD_LD14 = PAD_ID(PA, 20),
MX21_PAD_LD15 = PAD_ID(PA, 21),
MX21_PAD_LD16 = PAD_ID(PA, 22),
MX21_PAD_LD17 = PAD_ID(PA, 23),
MX21_PAD_REV = PAD_ID(PA, 24),
MX21_PAD_CLS = PAD_ID(PA, 25),
MX21_PAD_PS = PAD_ID(PA, 26),
MX21_PAD_SPL_SPR = PAD_ID(PA, 27),
MX21_PAD_HSYNC = PAD_ID(PA, 28),
MX21_PAD_VSYNC = PAD_ID(PA, 29),
MX21_PAD_CONTRAST = PAD_ID(PA, 30),
MX21_PAD_OE_ACD = PAD_ID(PA, 31),
MX21_PAD_SD2_D0 = PAD_ID(PB, 4),
MX21_PAD_SD2_D1 = PAD_ID(PB, 5),
MX21_PAD_SD2_D2 = PAD_ID(PB, 6),
MX21_PAD_SD2_D3 = PAD_ID(PB, 7),
MX21_PAD_SD2_CMD = PAD_ID(PB, 8),
MX21_PAD_SD2_CLK = PAD_ID(PB, 9),
MX21_PAD_CSI_D0 = PAD_ID(PB, 10),
MX21_PAD_CSI_D1 = PAD_ID(PB, 11),
MX21_PAD_CSI_D2 = PAD_ID(PB, 12),
MX21_PAD_CSI_D3 = PAD_ID(PB, 13),
MX21_PAD_CSI_D4 = PAD_ID(PB, 14),
MX21_PAD_CSI_MCLK = PAD_ID(PB, 15),
MX21_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
MX21_PAD_CSI_D5 = PAD_ID(PB, 17),
MX21_PAD_CSI_D6 = PAD_ID(PB, 18),
MX21_PAD_CSI_D7 = PAD_ID(PB, 19),
MX21_PAD_CSI_VSYNC = PAD_ID(PB, 20),
MX21_PAD_CSI_HSYNC = PAD_ID(PB, 21),
MX21_PAD_USB_BYP = PAD_ID(PB, 22),
MX21_PAD_USB_PWR = PAD_ID(PB, 23),
MX21_PAD_USB_OC = PAD_ID(PB, 24),
MX21_PAD_USBH_ON = PAD_ID(PB, 25),
MX21_PAD_USBH1_FS = PAD_ID(PB, 26),
MX21_PAD_USBH1_OE = PAD_ID(PB, 27),
MX21_PAD_USBH1_TXDM = PAD_ID(PB, 28),
MX21_PAD_USBH1_TXDP = PAD_ID(PB, 29),
MX21_PAD_USBH1_RXDM = PAD_ID(PB, 30),
MX21_PAD_USBH1_RXDP = PAD_ID(PB, 31),
MX21_PAD_USBG_SDA = PAD_ID(PC, 5),
MX21_PAD_USBG_SCL = PAD_ID(PC, 6),
MX21_PAD_USBG_ON = PAD_ID(PC, 7),
MX21_PAD_USBG_FS = PAD_ID(PC, 8),
MX21_PAD_USBG_OE = PAD_ID(PC, 9),
MX21_PAD_USBG_TXDM = PAD_ID(PC, 10),
MX21_PAD_USBG_TXDP = PAD_ID(PC, 11),
MX21_PAD_USBG_RXDM = PAD_ID(PC, 12),
MX21_PAD_USBG_RXDP = PAD_ID(PC, 13),
MX21_PAD_TOUT = PAD_ID(PC, 14),
MX21_PAD_TIN = PAD_ID(PC, 15),
MX21_PAD_SAP_FS = PAD_ID(PC, 16),
MX21_PAD_SAP_RXD = PAD_ID(PC, 17),
MX21_PAD_SAP_TXD = PAD_ID(PC, 18),
MX21_PAD_SAP_CLK = PAD_ID(PC, 19),
MX21_PAD_SSI1_FS = PAD_ID(PC, 20),
MX21_PAD_SSI1_RXD = PAD_ID(PC, 21),
MX21_PAD_SSI1_TXD = PAD_ID(PC, 22),
MX21_PAD_SSI1_CLK = PAD_ID(PC, 23),
MX21_PAD_SSI2_FS = PAD_ID(PC, 24),
MX21_PAD_SSI2_RXD = PAD_ID(PC, 25),
MX21_PAD_SSI2_TXD = PAD_ID(PC, 26),
MX21_PAD_SSI2_CLK = PAD_ID(PC, 27),
MX21_PAD_SSI3_FS = PAD_ID(PC, 28),
MX21_PAD_SSI3_RXD = PAD_ID(PC, 29),
MX21_PAD_SSI3_TXD = PAD_ID(PC, 30),
MX21_PAD_SSI3_CLK = PAD_ID(PC, 31),
MX21_PAD_I2C_DATA = PAD_ID(PD, 17),
MX21_PAD_I2C_CLK = PAD_ID(PD, 18),
MX21_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
MX21_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
MX21_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
MX21_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
MX21_PAD_CSPI2_MISO = PAD_ID(PD, 23),
MX21_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
MX21_PAD_CSPI1_RDY = PAD_ID(PD, 25),
MX21_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
MX21_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
MX21_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
MX21_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
MX21_PAD_CSPI1_MISO = PAD_ID(PD, 30),
MX21_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
MX21_PAD_TEST_WB2 = PAD_ID(PE, 0),
MX21_PAD_TEST_WB1 = PAD_ID(PE, 1),
MX21_PAD_TEST_WB0 = PAD_ID(PE, 2),
MX21_PAD_UART2_CTS = PAD_ID(PE, 3),
MX21_PAD_UART2_RTS = PAD_ID(PE, 4),
MX21_PAD_PWMO = PAD_ID(PE, 5),
MX21_PAD_UART2_TXD = PAD_ID(PE, 6),
MX21_PAD_UART2_RXD = PAD_ID(PE, 7),
MX21_PAD_UART3_TXD = PAD_ID(PE, 8),
MX21_PAD_UART3_RXD = PAD_ID(PE, 9),
MX21_PAD_UART3_CTS = PAD_ID(PE, 10),
MX21_PAD_UART3_RTS = PAD_ID(PE, 11),
MX21_PAD_UART1_TXD = PAD_ID(PE, 12),
MX21_PAD_UART1_RXD = PAD_ID(PE, 13),
MX21_PAD_UART1_CTS = PAD_ID(PE, 14),
MX21_PAD_UART1_RTS = PAD_ID(PE, 15),
MX21_PAD_RTCK = PAD_ID(PE, 16),
MX21_PAD_RESET_OUT = PAD_ID(PE, 17),
MX21_PAD_SD1_D0 = PAD_ID(PE, 18),
MX21_PAD_SD1_D1 = PAD_ID(PE, 19),
MX21_PAD_SD1_D2 = PAD_ID(PE, 20),
MX21_PAD_SD1_D3 = PAD_ID(PE, 21),
MX21_PAD_SD1_CMD = PAD_ID(PE, 22),
MX21_PAD_SD1_CLK = PAD_ID(PE, 23),
MX21_PAD_NFRB = PAD_ID(PF, 0),
MX21_PAD_NFCE = PAD_ID(PF, 1),
MX21_PAD_NFWP = PAD_ID(PF, 2),
MX21_PAD_NFCLE = PAD_ID(PF, 3),
MX21_PAD_NFALE = PAD_ID(PF, 4),
MX21_PAD_NFRE = PAD_ID(PF, 5),
MX21_PAD_NFWE = PAD_ID(PF, 6),
MX21_PAD_NFIO0 = PAD_ID(PF, 7),
MX21_PAD_NFIO1 = PAD_ID(PF, 8),
MX21_PAD_NFIO2 = PAD_ID(PF, 9),
MX21_PAD_NFIO3 = PAD_ID(PF, 10),
MX21_PAD_NFIO4 = PAD_ID(PF, 11),
MX21_PAD_NFIO5 = PAD_ID(PF, 12),
MX21_PAD_NFIO6 = PAD_ID(PF, 13),
MX21_PAD_NFIO7 = PAD_ID(PF, 14),
MX21_PAD_CLKO = PAD_ID(PF, 15),
MX21_PAD_RESERVED = PAD_ID(PF, 16),
MX21_PAD_CS4 = PAD_ID(PF, 21),
MX21_PAD_CS5 = PAD_ID(PF, 22),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
IMX_PINCTRL_PIN(MX21_PAD_LD0),
IMX_PINCTRL_PIN(MX21_PAD_LD1),
IMX_PINCTRL_PIN(MX21_PAD_LD2),
IMX_PINCTRL_PIN(MX21_PAD_LD3),
IMX_PINCTRL_PIN(MX21_PAD_LD4),
IMX_PINCTRL_PIN(MX21_PAD_LD5),
IMX_PINCTRL_PIN(MX21_PAD_LD6),
IMX_PINCTRL_PIN(MX21_PAD_LD7),
IMX_PINCTRL_PIN(MX21_PAD_LD8),
IMX_PINCTRL_PIN(MX21_PAD_LD9),
IMX_PINCTRL_PIN(MX21_PAD_LD10),
IMX_PINCTRL_PIN(MX21_PAD_LD11),
IMX_PINCTRL_PIN(MX21_PAD_LD12),
IMX_PINCTRL_PIN(MX21_PAD_LD13),
IMX_PINCTRL_PIN(MX21_PAD_LD14),
IMX_PINCTRL_PIN(MX21_PAD_LD15),
IMX_PINCTRL_PIN(MX21_PAD_LD16),
IMX_PINCTRL_PIN(MX21_PAD_LD17),
IMX_PINCTRL_PIN(MX21_PAD_REV),
IMX_PINCTRL_PIN(MX21_PAD_CLS),
IMX_PINCTRL_PIN(MX21_PAD_PS),
IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
IMX_PINCTRL_PIN(MX21_PAD_TOUT),
IMX_PINCTRL_PIN(MX21_PAD_TIN),
IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
IMX_PINCTRL_PIN(MX21_PAD_PWMO),
IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
IMX_PINCTRL_PIN(MX21_PAD_RTCK),
IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
IMX_PINCTRL_PIN(MX21_PAD_NFRB),
IMX_PINCTRL_PIN(MX21_PAD_NFCE),
IMX_PINCTRL_PIN(MX21_PAD_NFWP),
IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
IMX_PINCTRL_PIN(MX21_PAD_NFALE),
IMX_PINCTRL_PIN(MX21_PAD_NFRE),
IMX_PINCTRL_PIN(MX21_PAD_NFWE),
IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
IMX_PINCTRL_PIN(MX21_PAD_CLKO),
IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
IMX_PINCTRL_PIN(MX21_PAD_CS4),
IMX_PINCTRL_PIN(MX21_PAD_CS5),
};
static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
.pins = imx21_pinctrl_pads,
.npins = ARRAY_SIZE(imx21_pinctrl_pads),
};
static int __init imx21_pinctrl_probe(struct platform_device *pdev)
{
return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
}
static const struct of_device_id imx21_pinctrl_of_match[] = {
{ .compatible = "fsl,imx21-iomuxc", },
{ }
};
MODULE_DEVICE_TABLE(of, imx21_pinctrl_of_match);
static struct platform_driver imx21_pinctrl_driver = {
.driver = {
.name = "imx21-pinctrl",
.owner = THIS_MODULE,
.of_match_table = imx21_pinctrl_of_match,
},
.remove = imx1_pinctrl_core_remove,
};
module_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);
MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("Freescale i.MX21 pinctrl driver");
MODULE_LICENSE("GPL");

2
drivers/pinctrl/pinctrl-imx23.c → drivers/pinctrl/freescale/pinctrl-imx23.c
View File

@ -272,7 +272,7 @@ static int imx23_pinctrl_probe(struct platform_device *pdev)
return mxs_pinctrl_probe(pdev, &imx23_pinctrl_data);
}
static struct of_device_id imx23_pinctrl_of_match[] = {
static const struct of_device_id imx23_pinctrl_of_match[] = {
{ .compatible = "fsl,imx23-pinctrl", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx25.c → drivers/pinctrl/freescale/pinctrl-imx25.c
View File

@ -315,7 +315,7 @@ static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
.npins = ARRAY_SIZE(imx25_pinctrl_pads),
};
static struct of_device_id imx25_pinctrl_of_match[] = {
static const struct of_device_id imx25_pinctrl_of_match[] = {
{ .compatible = "fsl,imx25-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx27.c → drivers/pinctrl/freescale/pinctrl-imx27.c
View File

@ -389,7 +389,7 @@ static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
.npins = ARRAY_SIZE(imx27_pinctrl_pads),
};
static struct of_device_id imx27_pinctrl_of_match[] = {
static const struct of_device_id imx27_pinctrl_of_match[] = {
{ .compatible = "fsl,imx27-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx28.c → drivers/pinctrl/freescale/pinctrl-imx28.c
View File

@ -388,7 +388,7 @@ static int imx28_pinctrl_probe(struct platform_device *pdev)
return mxs_pinctrl_probe(pdev, &imx28_pinctrl_data);
}
static struct of_device_id imx28_pinctrl_of_match[] = {
static const struct of_device_id imx28_pinctrl_of_match[] = {
{ .compatible = "fsl,imx28-pinctrl", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx35.c → drivers/pinctrl/freescale/pinctrl-imx35.c
View File

@ -1005,7 +1005,7 @@ static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
.npins = ARRAY_SIZE(imx35_pinctrl_pads),
};
static struct of_device_id imx35_pinctrl_of_match[] = {
static const struct of_device_id imx35_pinctrl_of_match[] = {
{ .compatible = "fsl,imx35-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx50.c → drivers/pinctrl/freescale/pinctrl-imx50.c
View File

@ -391,7 +391,7 @@ static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
};
static struct of_device_id imx50_pinctrl_of_match[] = {
static const struct of_device_id imx50_pinctrl_of_match[] = {
{ .compatible = "fsl,imx50-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx51.c → drivers/pinctrl/freescale/pinctrl-imx51.c
View File

@ -768,7 +768,7 @@ static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
.npins = ARRAY_SIZE(imx51_pinctrl_pads),
};
static struct of_device_id imx51_pinctrl_of_match[] = {
static const struct of_device_id imx51_pinctrl_of_match[] = {
{ .compatible = "fsl,imx51-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx53.c → drivers/pinctrl/freescale/pinctrl-imx53.c
View File

@ -454,7 +454,7 @@ static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
.npins = ARRAY_SIZE(imx53_pinctrl_pads),
};
static struct of_device_id imx53_pinctrl_of_match[] = {
static const struct of_device_id imx53_pinctrl_of_match[] = {
{ .compatible = "fsl,imx53-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx6dl.c → drivers/pinctrl/freescale/pinctrl-imx6dl.c
View File

@ -460,7 +460,7 @@ static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
.npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
};
static struct of_device_id imx6dl_pinctrl_of_match[] = {
static const struct of_device_id imx6dl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6dl-iomuxc", },
{ /* sentinel */ }
};

2
drivers/pinctrl/pinctrl-imx6q.c → drivers/pinctrl/freescale/pinctrl-imx6q.c
View File

@ -466,7 +466,7 @@ static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
};
static struct of_device_id imx6q_pinctrl_of_match[] = {
static const struct of_device_id imx6q_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6q-iomuxc", },
{ /* sentinel */ }
};

3
drivers/pinctrl/pinctrl-imx6sl.c → drivers/pinctrl/freescale/pinctrl-imx6sl.c
View File

@ -366,10 +366,11 @@ static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
.npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
};
static struct of_device_id imx6sl_pinctrl_of_match[] = {
static const struct of_device_id imx6sl_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sl-iomuxc", },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx6sl_pinctrl_of_match);
static int imx6sl_pinctrl_probe(struct platform_device *pdev)
{

2
drivers/pinctrl/pinctrl-imx6sx.c → drivers/pinctrl/freescale/pinctrl-imx6sx.c
View File

@ -370,7 +370,7 @@ static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
.npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
};
static struct of_device_id imx6sx_pinctrl_of_match[] = {
static const struct of_device_id imx6sx_pinctrl_of_match[] = {
{ .compatible = "fsl,imx6sx-iomuxc", },
{ /* sentinel */ }
};

8
drivers/pinctrl/pinctrl-mxs.c → drivers/pinctrl/freescale/pinctrl-mxs.c
View File

@ -21,7 +21,7 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "core.h"
#include "../core.h"
#include "pinctrl-mxs.h"
#define SUFFIX_LEN 4
@ -195,8 +195,8 @@ static int mxs_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int mxs_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct mxs_pinctrl_data *d = pinctrl_dev_get_drvdata(pctldev);
struct mxs_group *g = &d->soc->groups[group];
@ -223,7 +223,7 @@ static const struct pinmux_ops mxs_pinmux_ops = {
.get_functions_count = mxs_pinctrl_get_funcs_count,
.get_function_name = mxs_pinctrl_get_func_name,
.get_function_groups = mxs_pinctrl_get_func_groups,
.enable = mxs_pinctrl_enable,
.set_mux = mxs_pinctrl_set_mux,
};
static int mxs_pinconf_get(struct pinctrl_dev *pctldev,

0
drivers/pinctrl/pinctrl-mxs.h → drivers/pinctrl/freescale/pinctrl-mxs.h
View File

2
drivers/pinctrl/pinctrl-vf610.c → drivers/pinctrl/freescale/pinctrl-vf610.c
View File

@ -299,7 +299,7 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
.pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
.flags = SHARE_MUX_CONF_REG,
};
static struct of_device_id vf610_pinctrl_of_match[] = {

6
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View File

@ -259,8 +259,8 @@ static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
return 0;
}
static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
unsigned gid)
static int mvebu_pinmux_set(struct pinctrl_dev *pctldev, unsigned fid,
unsigned gid)
{
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct mvebu_pinctrl_function *func = &pctl->functions[fid];
@ -344,7 +344,7 @@ static const struct pinmux_ops mvebu_pinmux_ops = {
.get_function_groups = mvebu_pinmux_get_groups,
.gpio_request_enable = mvebu_pinmux_gpio_request_enable,
.gpio_set_direction = mvebu_pinmux_gpio_set_direction,
.enable = mvebu_pinmux_enable,
.set_mux = mvebu_pinmux_set,
};
static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)

99
drivers/pinctrl/nomadik/pinctrl-abx500.c
View File

@ -34,6 +34,7 @@
#include "pinctrl-abx500.h"
#include "../core.h"
#include "../pinconf.h"
#include "../pinctrl-utils.h"
/*
* The AB9540 and AB8540 GPIO support are extended versions
@ -708,8 +709,8 @@ static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
static int abx500_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
struct gpio_chip *chip = &pct->chip;
@ -783,7 +784,7 @@ static const struct pinmux_ops abx500_pinmux_ops = {
.get_functions_count = abx500_pmx_get_funcs_cnt,
.get_function_name = abx500_pmx_get_func_name,
.get_function_groups = abx500_pmx_get_func_groups,
.enable = abx500_pmx_enable,
.set_mux = abx500_pmx_set,
.gpio_request_enable = abx500_gpio_request_enable,
.gpio_disable_free = abx500_gpio_disable_free,
};
@ -826,41 +827,6 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
chip->base + offset - 1);
}
static void abx500_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree(map[i].data.configs.configs);
kfree(map);
}
static int abx500_dt_reserve_map(struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps,
unsigned reserve)
{
unsigned old_num = *reserved_maps;
unsigned new_num = *num_maps + reserve;
struct pinctrl_map *new_map;
if (old_num >= new_num)
return 0;
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
if (!new_map)
return -ENOMEM;
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
*map = new_map;
*reserved_maps = new_num;
return 0;
}
static int abx500_dt_add_map_mux(struct pinctrl_map **map,
unsigned *reserved_maps,
unsigned *num_maps, const char *group,
@ -926,19 +892,32 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
unsigned long *configs;
unsigned int nconfigs = 0;
bool has_config = 0;
unsigned reserve = 0;
struct property *prop;
const char *group, *gpio_name;
struct device_node *np_config;
ret = of_property_read_string(np, "ste,function", &function);
if (ret >= 0)
reserve = 1;
if (ret >= 0) {
ret = of_property_count_strings(np, "ste,pins");
if (ret < 0)
goto exit;
ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
num_maps, ret);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
ret = abx500_dt_add_map_mux(map, reserved_maps,
num_maps, group, function);
if (ret < 0)
goto exit;
}
}
ret = pinconf_generic_parse_dt_config(np, &configs, &nconfigs);
if (nconfigs)
has_config = 1;
np_config = of_parse_phandle(np, "ste,config", 0);
if (np_config) {
ret = pinconf_generic_parse_dt_config(np_config, &configs,
@ -947,28 +926,18 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
goto exit;
has_config |= nconfigs;
}
if (has_config) {
ret = of_property_count_strings(np, "ste,pins");
if (ret < 0)
goto exit;
ret = of_property_count_strings(np, "ste,pins");
if (ret < 0)
goto exit;
ret = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps,
num_maps, ret);
if (ret < 0)
goto exit;
if (has_config)
reserve++;
reserve *= ret;
ret = abx500_dt_reserve_map(map, reserved_maps, num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
if (function) {
ret = abx500_dt_add_map_mux(map, reserved_maps,
num_maps, group, function);
if (ret < 0)
goto exit;
}
if (has_config) {
of_property_for_each_string(np, "ste,pins", prop, group) {
gpio_name = abx500_find_pin_name(pctldev, group);
ret = abx500_dt_add_map_configs(map, reserved_maps,
@ -976,8 +945,8 @@ static int abx500_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0)
goto exit;
}
}
exit:
return ret;
}
@ -998,7 +967,7 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev,
ret = abx500_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
abx500_dt_free_map(pctldev, *map, *num_maps);
pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
@ -1012,7 +981,7 @@ static const struct pinctrl_ops abx500_pinctrl_ops = {
.get_group_pins = abx500_get_group_pins,
.pin_dbg_show = abx500_pin_dbg_show,
.dt_node_to_map = abx500_dt_node_to_map,
.dt_free_map = abx500_dt_free_map,
.dt_free_map = pinctrl_utils_dt_free_map,
};
static int abx500_pin_config_get(struct pinctrl_dev *pctldev,

138
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View File

@ -32,6 +32,7 @@
#include <linux/pinctrl/consumer.h>
#include "pinctrl-nomadik.h"
#include "../core.h"
#include "../pinctrl-utils.h"
/*
* The GPIO module in the Nomadik family of Systems-on-Chip is an
@ -985,6 +986,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
container_of(chip, struct nmk_gpio_chip, chip);
int mode;
bool is_out;
bool data_out;
bool pull;
u32 bit = 1 << offset;
const char *modes[] = {
@ -997,28 +999,41 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
[NMK_GPIO_ALT_C+3] = "altC3",
[NMK_GPIO_ALT_C+4] = "altC4",
};
const char *pulls[] = {
"none ",
"pull down",
"pull up ",
};
clk_enable(nmk_chip->clk);
is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & bit);
mode = nmk_gpio_get_mode(gpio);
if ((mode == NMK_GPIO_ALT_C) && pctldev)
mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
gpio, label ?: "(none)",
is_out ? "out" : "in ",
chip->get
? (chip->get(chip, offset) ? "hi" : "lo")
: "? ",
(mode < 0) ? "unknown" : modes[mode],
pull ? "pull" : "none");
if (!is_out) {
if (is_out) {
seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
gpio,
label ?: "(none)",
data_out ? "hi" : "lo",
(mode < 0) ? "unknown" : modes[mode]);
} else {
int irq = gpio_to_irq(gpio);
struct irq_desc *desc = irq_to_desc(irq);
int pullidx = 0;
/* This races with request_irq(), set_irq_type(),
if (pull)
pullidx = data_out ? 1 : 2;
seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
gpio,
label ?: "(none)",
pulls[pullidx],
(mode < 0) ? "unknown" : modes[mode]);
/*
* This races with request_irq(), set_irq_type(),
* and set_irq_wake() ... but those are "rare".
*/
if (irq > 0 && desc && desc->action) {
@ -1338,39 +1353,6 @@ static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
}
static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
int i;
for (i = 0; i < num_maps; i++)
if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
kfree(map[i].data.configs.configs);
kfree(map);
}
static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, unsigned reserve)
{
unsigned old_num = *reserved_maps;
unsigned new_num = *num_maps + reserve;
struct pinctrl_map *new_map;
if (old_num >= new_num)
return 0;
new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
if (!new_map)
return -ENOMEM;
memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
*map = new_map;
*reserved_maps = new_num;
return 0;
}
static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
unsigned *num_maps, const char *group,
const char *function)
@ -1537,51 +1519,55 @@ static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
const char *function = NULL;
unsigned long configs = 0;
bool has_config = 0;
unsigned reserve = 0;
struct property *prop;
const char *group, *gpio_name;
struct device_node *np_config;
ret = of_property_read_string(np, "ste,function", &function);
if (ret >= 0)
reserve = 1;
if (ret >= 0) {
ret = of_property_count_strings(np, "ste,pins");
if (ret < 0)
goto exit;
has_config = nmk_pinctrl_dt_get_config(np, &configs);
ret = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps,
num_maps, ret);
if (ret < 0)
goto exit;
np_config = of_parse_phandle(np, "ste,config", 0);
if (np_config)
has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
ret = of_property_count_strings(np, "ste,pins");
if (ret < 0)
goto exit;
if (has_config)
reserve++;
reserve *= ret;
ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
if (function) {
of_property_for_each_string(np, "ste,pins", prop, group) {
ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
group, function);
if (ret < 0)
goto exit;
}
if (has_config) {
}
has_config = nmk_pinctrl_dt_get_config(np, &configs);
np_config = of_parse_phandle(np, "ste,config", 0);
if (np_config)
has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
if (has_config) {
ret = of_property_count_strings(np, "ste,pins");
if (ret < 0)
goto exit;
ret = pinctrl_utils_reserve_map(pctldev, map,
reserved_maps,
num_maps, ret);
if (ret < 0)
goto exit;
of_property_for_each_string(np, "ste,pins", prop, group) {
gpio_name = nmk_find_pin_name(pctldev, group);
ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
gpio_name, &configs, 1);
ret = nmk_dt_add_map_configs(map, reserved_maps,
num_maps,
gpio_name, &configs, 1);
if (ret < 0)
goto exit;
}
}
exit:
return ret;
}
@ -1602,7 +1588,7 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
&reserved_maps, num_maps);
if (ret < 0) {
nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
return ret;
}
}
@ -1616,7 +1602,7 @@ static const struct pinctrl_ops nmk_pinctrl_ops = {
.get_group_pins = nmk_get_group_pins,
.pin_dbg_show = nmk_pin_dbg_show,
.dt_node_to_map = nmk_pinctrl_dt_node_to_map,
.dt_free_map = nmk_pinctrl_dt_free_map,
.dt_free_map = pinctrl_utils_dt_free_map,
};
static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
@ -1647,8 +1633,8 @@ static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
const struct nmk_pingroup *g;
@ -1810,7 +1796,7 @@ static const struct pinmux_ops nmk_pinmux_ops = {
.get_functions_count = nmk_pmx_get_funcs_cnt,
.get_function_name = nmk_pmx_get_func_name,
.get_function_groups = nmk_pmx_get_func_groups,
.enable = nmk_pmx_enable,
.set_mux = nmk_pmx_set,
.gpio_request_enable = nmk_gpio_request_enable,
.gpio_disable_free = nmk_gpio_disable_free,
};

7
drivers/pinctrl/pinctrl-adi2.c
View File

@ -619,8 +619,8 @@ static struct pinctrl_ops adi_pctrl_ops = {
.get_group_pins = adi_get_group_pins,
};
static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned func_id,
unsigned group_id)
static int adi_pinmux_set(struct pinctrl_dev *pctldev, unsigned func_id,
unsigned group_id)
{
struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
struct gpio_port *port;
@ -698,7 +698,7 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
}
static struct pinmux_ops adi_pinmux_ops = {
.enable = adi_pinmux_enable,
.set_mux = adi_pinmux_set,
.get_functions_count = adi_pinmux_get_funcs_count,
.get_function_name = adi_pinmux_get_func_name,
.get_function_groups = adi_pinmux_get_groups,
@ -1041,7 +1041,6 @@ static int adi_gpio_remove(struct platform_device *pdev)
u8 offset;
list_del(&port->node);
gpiochip_remove_pin_ranges(&port->chip);
gpiochip_remove(&port->chip);
if (port->pint) {
for (offset = 0; offset < port->width; offset++)

4
drivers/pinctrl/pinctrl-as3722.c
View File

@ -230,7 +230,7 @@ static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
static int as3722_pinctrl_set(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
@ -327,7 +327,7 @@ static const struct pinmux_ops as3722_pinmux_ops = {
.get_functions_count = as3722_pinctrl_get_funcs_count,
.get_function_name = as3722_pinctrl_get_func_name,
.get_function_groups = as3722_pinctrl_get_func_groups,
.enable = as3722_pinctrl_enable,
.set_mux = as3722_pinctrl_set,
.gpio_request_enable = as3722_pinctrl_gpio_request_enable,
.gpio_set_direction = as3722_pinctrl_gpio_set_direction,
};

212
drivers/pinctrl/pinctrl-at91.c
View File

@ -58,10 +58,27 @@ static int gpio_banks;
#define DEGLITCH (1 << 2)
#define PULL_DOWN (1 << 3)
#define DIS_SCHMIT (1 << 4)
#define DRIVE_STRENGTH_SHIFT 5
#define DRIVE_STRENGTH_MASK 0x3
#define DRIVE_STRENGTH (DRIVE_STRENGTH_MASK << DRIVE_STRENGTH_SHIFT)
#define DEBOUNCE (1 << 16)
#define DEBOUNCE_VAL_SHIFT 17
#define DEBOUNCE_VAL (0x3fff << DEBOUNCE_VAL_SHIFT)
/**
* These defines will translated the dt binding settings to our internal
* settings. They are not necessarily the same value as the register setting.
* The actual drive strength current of low, medium and high must be looked up
* from the corresponding device datasheet. This value is different for pins
* that are even in the same banks. It is also dependent on VCC.
* DRIVE_STRENGTH_DEFAULT is just a placeholder to avoid changing the drive
* strength when there is no dt config for it.
*/
#define DRIVE_STRENGTH_DEFAULT (0 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_LOW (1 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_MED (2 << DRIVE_STRENGTH_SHIFT)
#define DRIVE_STRENGTH_HI (3 << DRIVE_STRENGTH_SHIFT)
/**
* struct at91_pmx_func - describes AT91 pinmux functions
* @name: the name of this specific function
@ -148,6 +165,9 @@ struct at91_pinctrl_mux_ops {
void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
void (*set_drivestrength)(void __iomem *pio, unsigned pin,
u32 strength);
/* irq */
int (*irq_type)(struct irq_data *d, unsigned type);
};
@ -315,6 +335,30 @@ static unsigned pin_to_mask(unsigned int pin)
return 1 << pin;
}
static unsigned two_bit_pin_value_shift_amount(unsigned int pin)
{
/* return the shift value for a pin for "two bit" per pin registers,
* i.e. drive strength */
return 2*((pin >= MAX_NB_GPIO_PER_BANK/2)
? pin - MAX_NB_GPIO_PER_BANK/2 : pin);
}
static unsigned sama5d3_get_drive_register(unsigned int pin)
{
/* drive strength is split between two registers
* with two bits per pin */
return (pin >= MAX_NB_GPIO_PER_BANK/2)
? SAMA5D3_PIO_DRIVER2 : SAMA5D3_PIO_DRIVER1;
}
static unsigned at91sam9x5_get_drive_register(unsigned int pin)
{
/* drive strength is split between two registers
* with two bits per pin */
return (pin >= MAX_NB_GPIO_PER_BANK/2)
? AT91SAM9X5_PIO_DRIVER2 : AT91SAM9X5_PIO_DRIVER1;
}
static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask)
{
writel_relaxed(mask, pio + PIO_IDR);
@ -327,6 +371,9 @@ static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin)
static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
{
if (on)
writel_relaxed(mask, pio + PIO_PPDDR);
writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR));
}
@ -455,6 +502,9 @@ static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
{
if (is_on)
__raw_writel(mask, pio + PIO_PUDR);
__raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
}
@ -468,6 +518,79 @@ static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1;
}
static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
{
unsigned tmp = __raw_readl(reg);
tmp = tmp >> two_bit_pin_value_shift_amount(pin);
return tmp & DRIVE_STRENGTH_MASK;
}
static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio,
unsigned pin)
{
unsigned tmp = read_drive_strength(pio +
sama5d3_get_drive_register(pin), pin);
/* SAMA5 strength is 1:1 with our defines,
* except 0 is equivalent to low per datasheet */
if (!tmp)
tmp = DRIVE_STRENGTH_LOW;
return tmp;
}
static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
unsigned pin)
{
unsigned tmp = read_drive_strength(pio +
at91sam9x5_get_drive_register(pin), pin);
/* strength is inverse in SAM9x5s hardware with the pinctrl defines
* hardware: 0 = hi, 1 = med, 2 = low, 3 = rsvd */
tmp = DRIVE_STRENGTH_HI - tmp;
return tmp;
}
static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
{
unsigned tmp = __raw_readl(reg);
unsigned shift = two_bit_pin_value_shift_amount(pin);
tmp &= ~(DRIVE_STRENGTH_MASK << shift);
tmp |= strength << shift;
__raw_writel(tmp, reg);
}
static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
u32 setting)
{
/* do nothing if setting is zero */
if (!setting)
return;
/* strength is 1 to 1 with setting for SAMA5 */
set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting);
}
static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin,
u32 setting)
{
/* do nothing if setting is zero */
if (!setting)
return;
/* strength is inverse on SAM9x5s with our defines
* 0 = hi, 1 = med, 2 = low, 3 = rsvd */
setting = DRIVE_STRENGTH_HI - setting;
set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin,
setting);
}
static struct at91_pinctrl_mux_ops at91rm9200_ops = {
.get_periph = at91_mux_get_periph,
.mux_A_periph = at91_mux_set_A_periph,
@ -491,6 +614,27 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
.set_pulldown = at91_mux_pio3_set_pulldown,
.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sam9x5_get_drivestrength,
.set_drivestrength = at91_mux_sam9x5_set_drivestrength,
.irq_type = alt_gpio_irq_type,
};
static struct at91_pinctrl_mux_ops sama5d3_ops = {
.get_periph = at91_mux_pio3_get_periph,
.mux_A_periph = at91_mux_pio3_set_A_periph,
.mux_B_periph = at91_mux_pio3_set_B_periph,
.mux_C_periph = at91_mux_pio3_set_C_periph,
.mux_D_periph = at91_mux_pio3_set_D_periph,
.get_deglitch = at91_mux_pio3_get_deglitch,
.set_deglitch = at91_mux_pio3_set_deglitch,
.get_debounce = at91_mux_pio3_get_debounce,
.set_debounce = at91_mux_pio3_set_debounce,
.get_pulldown = at91_mux_pio3_get_pulldown,
.set_pulldown = at91_mux_pio3_set_pulldown,
.get_schmitt_trig = at91_mux_pio3_get_schmitt_trig,
.disable_schmitt_trig = at91_mux_pio3_disable_schmitt_trig,
.get_drivestrength = at91_mux_sama5d3_get_drivestrength,
.set_drivestrength = at91_mux_sama5d3_set_drivestrength,
.irq_type = alt_gpio_irq_type,
};
@ -554,8 +698,8 @@ static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input)
writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER));
}
static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int at91_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct at91_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf;
@ -684,7 +828,7 @@ static const struct pinmux_ops at91_pmx_ops = {
.get_functions_count = at91_pmx_get_funcs_count,
.get_function_name = at91_pmx_get_func_name,
.get_function_groups = at91_pmx_get_groups,
.enable = at91_pmx_enable,
.set_mux = at91_pmx_set,
.gpio_request_enable = at91_gpio_request_enable,
.gpio_disable_free = at91_gpio_disable_free,
};
@ -716,6 +860,9 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
*config |= PULL_DOWN;
if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin))
*config |= DIS_SCHMIT;
if (info->ops->get_drivestrength)
*config |= (info->ops->get_drivestrength(pio, pin)
<< DRIVE_STRENGTH_SHIFT);
return 0;
}
@ -729,6 +876,7 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
void __iomem *pio;
int i;
unsigned long config;
unsigned pin;
for (i = 0; i < num_configs; i++) {
config = configs[i];
@ -737,7 +885,8 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
"%s:%d, pin_id=%d, config=0x%lx",
__func__, __LINE__, pin_id, config);
pio = pin_to_controller(info, pin_to_bank(pin_id));
mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
pin = pin_id % MAX_NB_GPIO_PER_BANK;
mask = pin_to_mask(pin);
if (config & PULL_UP && config & PULL_DOWN)
return -EINVAL;
@ -753,6 +902,10 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
info->ops->set_pulldown(pio, mask, config & PULL_DOWN);
if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT)
info->ops->disable_schmitt_trig(pio, mask);
if (info->ops->set_drivestrength)
info->ops->set_drivestrength(pio, pin,
(config & DRIVE_STRENGTH)
>> DRIVE_STRENGTH_SHIFT);
} /* for each config */
@ -768,6 +921,15 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
} \
} while (0)
#define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
if ((config & mask) == flag) { \
if (num_conf) \
seq_puts(s, "|"); \
seq_puts(s, #flag); \
num_conf++; \
} \
} while (0)
static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
@ -781,6 +943,9 @@ static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
DBG_SHOW_FLAG(PULL_DOWN);
DBG_SHOW_FLAG(DIS_SCHMIT);
DBG_SHOW_FLAG(DEGLITCH);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_LOW);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_MED);
DBG_SHOW_FLAG_MASKED(DRIVE_STRENGTH, DRIVE_STRENGTH_HI);
DBG_SHOW_FLAG(DEBOUNCE);
if (config & DEBOUNCE) {
val = config >> DEBOUNCE_VAL_SHIFT;
@ -945,6 +1110,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
}
static struct of_device_id at91_pinctrl_of_match[] = {
{ .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
{ .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
{ .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
{ /* sentinel */ }
@ -1445,7 +1611,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
/* now it may re-trigger */
}
static int at91_gpio_of_irq_setup(struct device_node *node,
static int at91_gpio_of_irq_setup(struct platform_device *pdev,
struct at91_gpio_chip *at91_gpio)
{
struct at91_gpio_chip *prev = NULL;
@ -1470,9 +1636,11 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
0,
handle_edge_irq,
IRQ_TYPE_EDGE_BOTH);
if (ret)
panic("at91_gpio.%d: couldn't allocate irq domain (DT).\n",
if (ret) {
dev_err(&pdev->dev, "at91_gpio.%d: Couldn't add irqchip to gpiochip.\n",
at91_gpio->pioc_idx);
return ret;
}
/* Setup chained handler */
if (at91_gpio->pioc_idx)
@ -1575,19 +1743,22 @@ static int at91_gpio_probe(struct platform_device *pdev)
at91_chip->pioc_virq = irq;
at91_chip->pioc_idx = alias_idx;
at91_chip->clock = clk_get(&pdev->dev, NULL);
at91_chip->clock = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(at91_chip->clock)) {
dev_err(&pdev->dev, "failed to get clock, ignoring.\n");
ret = PTR_ERR(at91_chip->clock);
goto err;
}
if (clk_prepare(at91_chip->clock))
goto clk_prep_err;
ret = clk_prepare(at91_chip->clock);
if (ret)
goto clk_prepare_err;
/* enable PIO controller's clock */
if (clk_enable(at91_chip->clock)) {
ret = clk_enable(at91_chip->clock);
if (ret) {
dev_err(&pdev->dev, "failed to enable clock, ignoring.\n");
goto clk_err;
goto clk_enable_err;
}
at91_chip->chip = at91_gpio_template;
@ -1612,7 +1783,7 @@ static int at91_gpio_probe(struct platform_device *pdev)
if (!names) {
ret = -ENOMEM;
goto clk_err;
goto clk_enable_err;
}
for (i = 0; i < chip->ngpio; i++)
@ -1630,23 +1801,28 @@ static int at91_gpio_probe(struct platform_device *pdev)
ret = gpiochip_add(chip);
if (ret)
goto clk_err;
goto gpiochip_add_err;
gpio_chips[alias_idx] = at91_chip;
gpio_banks = max(gpio_banks, alias_idx + 1);
at91_gpio_probe_fixup();
at91_gpio_of_irq_setup(np, at91_chip);
ret = at91_gpio_of_irq_setup(pdev, at91_chip);
if (ret)
goto irq_setup_err;
dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase);
return 0;
clk_err:
irq_setup_err:
gpiochip_remove(chip);
gpiochip_add_err:
clk_disable(at91_chip->clock);
clk_enable_err:
clk_unprepare(at91_chip->clock);
clk_prep_err:
clk_put(at91_chip->clock);
clk_prepare_err:
err:
dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);

8
drivers/pinctrl/pinctrl-bcm281xx.c
View File

@ -1055,9 +1055,9 @@ static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int bcm281xx_pinmux_enable(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
const struct bcm281xx_pin_function *f = &pdata->functions[function];
@ -1084,7 +1084,7 @@ static struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
.get_functions_count = bcm281xx_pinctrl_get_fcns_count,
.get_function_name = bcm281xx_pinctrl_get_fcn_name,
.get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
.enable = bcm281xx_pinmux_enable,
.set_mux = bcm281xx_pinmux_set,
};
static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,

4
drivers/pinctrl/pinctrl-bcm2835.c
View File

@ -830,7 +830,7 @@ static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
unsigned func_selector,
unsigned group_selector)
{
@ -869,7 +869,7 @@ static const struct pinmux_ops bcm2835_pmx_ops = {
.get_functions_count = bcm2835_pmx_get_functions_count,
.get_function_name = bcm2835_pmx_get_function_name,
.get_function_groups = bcm2835_pmx_get_function_groups,
.enable = bcm2835_pmx_enable,
.set_mux = bcm2835_pmx_set,
.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
};

8
drivers/pinctrl/pinctrl-lantiq.c
View File

@ -257,9 +257,9 @@ static int match_group_mux(const struct ltq_pin_group *grp,
return ret;
}
static int ltq_pmx_enable(struct pinctrl_dev *pctrldev,
unsigned func,
unsigned group)
static int ltq_pmx_set(struct pinctrl_dev *pctrldev,
unsigned func,
unsigned group)
{
struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
const struct ltq_pin_group *pin_grp = &info->grps[group];
@ -316,7 +316,7 @@ static const struct pinmux_ops ltq_pmx_ops = {
.get_functions_count = ltq_pmx_func_count,
.get_function_name = ltq_pmx_func_name,
.get_function_groups = ltq_pmx_get_groups,
.enable = ltq_pmx_enable,
.set_mux = ltq_pmx_set,
.gpio_request_enable = ltq_pmx_gpio_request_enable,
};

5
drivers/pinctrl/pinctrl-palmas.c
View File

@ -685,7 +685,8 @@ static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
@ -742,7 +743,7 @@ static const struct pinmux_ops palmas_pinmux_ops = {
.get_functions_count = palmas_pinctrl_get_funcs_count,
.get_function_name = palmas_pinctrl_get_func_name,
.get_function_groups = palmas_pinctrl_get_func_groups,
.enable = palmas_pinctrl_enable,
.set_mux = palmas_pinctrl_set_mux,
};
static int palmas_pinconf_get(struct pinctrl_dev *pctldev,

6
drivers/pinctrl/pinctrl-rockchip.c
View File

@ -816,8 +816,8 @@ static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins = info->groups[group].pins;
@ -892,7 +892,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
.get_functions_count = rockchip_pmx_get_funcs_count,
.get_function_name = rockchip_pmx_get_func_name,
.get_function_groups = rockchip_pmx_get_groups,
.enable = rockchip_pmx_enable,
.set_mux = rockchip_pmx_set,
.gpio_set_direction = rockchip_pmx_gpio_set_direction,
};

18
drivers/pinctrl/pinctrl-single.c
View File

@ -447,7 +447,7 @@ static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
return 0;
}
static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
{
struct pcs_device *pcs;
@ -519,7 +519,7 @@ static const struct pinmux_ops pcs_pinmux_ops = {
.get_functions_count = pcs_get_functions_count,
.get_function_name = pcs_get_function_name,
.get_function_groups = pcs_get_function_groups,
.enable = pcs_enable,
.set_mux = pcs_set_mux,
.gpio_request_enable = pcs_request_gpio,
};
@ -1981,6 +1981,18 @@ static const struct pcs_soc_data pinctrl_single_omap_wkup = {
.irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
};
static const struct pcs_soc_data pinctrl_single_dra7 = {
.flags = PCS_QUIRK_SHARED_IRQ,
.irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
.irq_status_mask = (1 << 25), /* WAKEUPEVENT */
};
static const struct pcs_soc_data pinctrl_single_am437x = {
.flags = PCS_QUIRK_SHARED_IRQ,
.irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
.irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
};
static const struct pcs_soc_data pinctrl_single = {
};
@ -1992,6 +2004,8 @@ static struct of_device_id pcs_of_match[] = {
{ .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
{ .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
{ .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
{ .compatible = "pinctrl-single", .data = &pinctrl_single },
{ .compatible = "pinconf-single", .data = &pinconf_single },
{ },

7
drivers/pinctrl/pinctrl-st.c
View File

@ -914,8 +914,8 @@ static struct st_pio_control *st_get_pio_control(
return &bank->pc;
}
static int st_pmx_enable(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
{
struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
struct st_pinconf *conf = info->groups[group].pin_conf;
@ -951,7 +951,7 @@ static struct pinmux_ops st_pmxops = {
.get_functions_count = st_pmx_get_funcs_count,
.get_function_name = st_pmx_get_fname,
.get_function_groups = st_pmx_get_groups,
.enable = st_pmx_enable,
.set_mux = st_pmx_set_mux,
.gpio_set_direction = st_pmx_set_gpio_direction,
};
@ -1517,6 +1517,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
0, handle_simple_irq,
IRQ_TYPE_LEVEL_LOW);
if (err) {
gpiochip_remove(&bank->gpio_chip);
dev_info(dev, "could not add irqchip\n");
return err;
}

4
drivers/pinctrl/pinctrl-tb10x.c
View File

@ -697,7 +697,7 @@ static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
mutex_unlock(&state->mutex);
}
static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
unsigned func_selector, unsigned group_selector)
{
struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
@ -744,7 +744,7 @@ static struct pinmux_ops tb10x_pinmux_ops = {
.get_function_groups = tb10x_get_function_groups,
.gpio_request_enable = tb10x_gpio_request_enable,
.gpio_disable_free = tb10x_gpio_disable_free,
.enable = tb10x_pctl_enable,
.set_mux = tb10x_pctl_set_mux,
};
static struct pinctrl_desc tb10x_pindesc = {

8
drivers/pinctrl/pinctrl-tegra-xusb.c
View File

@ -281,9 +281,9 @@ static int tegra_xusb_padctl_get_function_groups(struct pinctrl_dev *pinctrl,
return 0;
}
static int tegra_xusb_padctl_pinmux_enable(struct pinctrl_dev *pinctrl,
unsigned int function,
unsigned int group)
static int tegra_xusb_padctl_pinmux_set(struct pinctrl_dev *pinctrl,
unsigned int function,
unsigned int group)
{
struct tegra_xusb_padctl *padctl = pinctrl_dev_get_drvdata(pinctrl);
const struct tegra_xusb_padctl_lane *lane;
@ -311,7 +311,7 @@ static const struct pinmux_ops tegra_xusb_padctl_pinmux_ops = {
.get_functions_count = tegra_xusb_padctl_get_functions_count,
.get_function_name = tegra_xusb_padctl_get_function_name,
.get_function_groups = tegra_xusb_padctl_get_function_groups,
.enable = tegra_xusb_padctl_pinmux_enable,
.set_mux = tegra_xusb_padctl_pinmux_set,
};
static int tegra_xusb_padctl_pinconf_group_get(struct pinctrl_dev *pinctrl,

7
drivers/pinctrl/pinctrl-tegra.c
View File

@ -262,8 +262,9 @@ static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tegra_pingroup *g;
@ -294,7 +295,7 @@ static const struct pinmux_ops tegra_pinmux_ops = {
.get_functions_count = tegra_pinctrl_get_funcs_count,
.get_function_name = tegra_pinctrl_get_func_name,
.get_function_groups = tegra_pinctrl_get_func_groups,
.enable = tegra_pinctrl_enable,
.set_mux = tegra_pinctrl_set_mux,
};
static int tegra_pinconf_reg(struct tegra_pmx *pmx,

2
drivers/pinctrl/pinctrl-tegra114.c
View File

@ -1850,7 +1850,7 @@ static int tegra114_pinctrl_probe(struct platform_device *pdev)
return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
}
static struct of_device_id tegra114_pinctrl_of_match[] = {
static const struct of_device_id tegra114_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra114-pinmux", },
{ },
};

69
drivers/pinctrl/pinctrl-tegra124.c
View File

@ -224,6 +224,16 @@
#define TEGRA_PIN_OWR _PIN(5)
#define TEGRA_PIN_CLK_32K_IN _PIN(6)
#define TEGRA_PIN_JTAG_RTCK _PIN(7)
#define TEGRA_PIN_DSI_B_CLK_P _PIN(8)
#define TEGRA_PIN_DSI_B_CLK_N _PIN(9)
#define TEGRA_PIN_DSI_B_D0_P _PIN(10)
#define TEGRA_PIN_DSI_B_D0_N _PIN(11)
#define TEGRA_PIN_DSI_B_D1_P _PIN(12)
#define TEGRA_PIN_DSI_B_D1_N _PIN(13)
#define TEGRA_PIN_DSI_B_D2_P _PIN(14)
#define TEGRA_PIN_DSI_B_D2_N _PIN(15)
#define TEGRA_PIN_DSI_B_D3_P _PIN(16)
#define TEGRA_PIN_DSI_B_D3_N _PIN(17)
static const struct pinctrl_pin_desc tegra124_pins[] = {
PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
@ -417,6 +427,16 @@ static const struct pinctrl_pin_desc tegra124_pins[] = {
PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
};
static const unsigned clk_32k_out_pa0_pins[] = {
@ -1495,6 +1515,19 @@ static const unsigned drive_ao4_pins[] = {
TEGRA_PIN_JTAG_RTCK,
};
static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
TEGRA_PIN_DSI_B_CLK_P,
TEGRA_PIN_DSI_B_CLK_N,
TEGRA_PIN_DSI_B_D0_P,
TEGRA_PIN_DSI_B_D0_N,
TEGRA_PIN_DSI_B_D1_P,
TEGRA_PIN_DSI_B_D1_N,
TEGRA_PIN_DSI_B_D2_P,
TEGRA_PIN_DSI_B_D2_N,
TEGRA_PIN_DSI_B_D3_P,
TEGRA_PIN_DSI_B_D3_N,
};
enum tegra_mux {
TEGRA_MUX_BLINK,
TEGRA_MUX_CCLA,
@ -1580,6 +1613,8 @@ enum tegra_mux {
TEGRA_MUX_VI_ALT3,
TEGRA_MUX_VIMCLK2,
TEGRA_MUX_VIMCLK2_ALT,
TEGRA_MUX_CSI,
TEGRA_MUX_DSI_B,
};
#define FUNCTION(fname) \
@ -1672,10 +1707,13 @@ static struct tegra_function tegra124_functions[] = {
FUNCTION(vi_alt3),
FUNCTION(vimclk2),
FUNCTION(vimclk2_alt),
FUNCTION(csi),
FUNCTION(dsi_b),
};
#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
#define PINGROUP_REG_A 0x3000 /* bank 1 */
#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
@ -1744,6 +1782,32 @@ static struct tegra_function tegra124_functions[] = {
.drvtype_bit = PINGROUP_BIT_##drvtype(6), \
}
#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
{ \
.name = "mipi_pad_ctrl_" #pg_name, \
.pins = mipi_pad_ctrl_##pg_name##_pins, \
.npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins), \
.funcs = { \
TEGRA_MUX_ ## f0, \
TEGRA_MUX_ ## f1, \
TEGRA_MUX_RSVD3, \
TEGRA_MUX_RSVD4, \
}, \
.mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r), \
.mux_bank = 2, \
.mux_bit = b, \
.pupd_reg = -1, \
.tri_reg = -1, \
.einput_bit = -1, \
.odrain_bit = -1, \
.lock_bit = -1, \
.ioreset_bit = -1, \
.rcv_sel_bit = -1, \
.drv_reg = -1, \
}
static const struct tegra_pingroup tegra124_groups[] = {
/* pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel */
PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N, N),
@ -1979,6 +2043,9 @@ static const struct tegra_pingroup tegra124_groups[] = {
DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
/* pg_name, r b f0, f1 */
MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B)
};
static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
@ -1996,7 +2063,7 @@ static int tegra124_pinctrl_probe(struct platform_device *pdev)
return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
}
static struct of_device_id tegra124_pinctrl_of_match[] = {
static const struct of_device_id tegra124_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra124-pinmux", },
{ },
};

2
drivers/pinctrl/pinctrl-tegra20.c
View File

@ -2228,7 +2228,7 @@ static int tegra20_pinctrl_probe(struct platform_device *pdev)
return tegra_pinctrl_probe(pdev, &tegra20_pinctrl);
}
static struct of_device_id tegra20_pinctrl_of_match[] = {
static const struct of_device_id tegra20_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra20-pinmux", },
{ },
};

2
drivers/pinctrl/pinctrl-tegra30.c
View File

@ -2484,7 +2484,7 @@ static int tegra30_pinctrl_probe(struct platform_device *pdev)
return tegra_pinctrl_probe(pdev, &tegra30_pinctrl);
}
static struct of_device_id tegra30_pinctrl_of_match[] = {
static const struct of_device_id tegra30_pinctrl_of_match[] = {
{ .compatible = "nvidia,tegra30-pinmux", },
{ },
};

7
drivers/pinctrl/pinctrl-tz1090-pdc.c
View File

@ -547,8 +547,9 @@ static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx,
__global_unlock2(flags);
}
static int tz1090_pdc_pinctrl_enable(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int function,
unsigned int group)
{
struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group];
@ -634,7 +635,7 @@ static struct pinmux_ops tz1090_pdc_pinmux_ops = {
.get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
.get_function_name = tz1090_pdc_pinctrl_get_func_name,
.get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
.enable = tz1090_pdc_pinctrl_enable,
.set_mux = tz1090_pdc_pinctrl_set_mux,
.gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable,
.gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free,
};

6
drivers/pinctrl/pinctrl-tz1090.c
View File

@ -1415,8 +1415,8 @@ found_mux:
* the effect is the same as enabling the function on each individual pin in the
* group.
*/
static int tz1090_pinctrl_enable(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev,
unsigned int function, unsigned int group)
{
struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
struct tz1090_pingroup *grp;
@ -1517,7 +1517,7 @@ static struct pinmux_ops tz1090_pinmux_ops = {
.get_functions_count = tz1090_pinctrl_get_funcs_count,
.get_function_name = tz1090_pinctrl_get_func_name,
.get_function_groups = tz1090_pinctrl_get_func_groups,
.enable = tz1090_pinctrl_enable,
.set_mux = tz1090_pinctrl_set_mux,
.gpio_request_enable = tz1090_pinctrl_gpio_request_enable,
.gpio_disable_free = tz1090_pinctrl_gpio_disable_free,
};

6
drivers/pinctrl/pinctrl-u300.c
View File

@ -955,8 +955,8 @@ static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
}
}
static int u300_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct u300_pmx *upmx;
@ -994,7 +994,7 @@ static const struct pinmux_ops u300_pmx_ops = {
.get_functions_count = u300_pmx_get_funcs_count,
.get_function_name = u300_pmx_get_func_name,
.get_function_groups = u300_pmx_get_groups,
.enable = u300_pmx_enable,
.set_mux = u300_pmx_set_mux,
};
static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,

2
drivers/pinctrl/pinctrl-xway.c
View File

@ -801,6 +801,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
of_gpiochip_add(&xway_chip);
ret = gpiochip_add(&xway_chip);
if (ret) {
of_gpiochip_remove(&xway_chip);
dev_err(&pdev->dev, "Failed to register gpio chip\n");
return ret;
}
@ -822,6 +823,7 @@ static int pinmux_xway_probe(struct platform_device *pdev)
/* register with the generic lantiq layer */
ret = ltq_pinctrl_register(pdev, &xway_info);
if (ret) {
gpiochip_remove(&xway_chip);
dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
return ret;
}

10
drivers/pinctrl/pinmux.c
View File

@ -41,7 +41,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
!ops->get_functions_count ||
!ops->get_function_name ||
!ops->get_function_groups ||
!ops->enable) {
!ops->set_mux) {
dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n");
return -EINVAL;
}
@ -445,15 +445,15 @@ int pinmux_enable_setting(struct pinctrl_setting const *setting)
desc->mux_setting = &(setting->data.mux);
}
ret = ops->enable(pctldev, setting->data.mux.func,
setting->data.mux.group);
ret = ops->set_mux(pctldev, setting->data.mux.func,
setting->data.mux.group);
if (ret)
goto err_enable;
goto err_set_mux;
return 0;
err_enable:
err_set_mux:
for (i = 0; i < num_pins; i++) {
desc = pin_desc_get(pctldev, pins[i]);
if (desc)

8
drivers/pinctrl/qcom/Kconfig
View File

@ -15,6 +15,14 @@ config PINCTRL_APQ8064
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
config PINCTRL_APQ8084
tristate "Qualcomm APQ8084 pin controller driver"
depends on GPIOLIB && OF
select PINCTRL_MSM
help
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm APQ8084 platform.
config PINCTRL_IPQ8064
tristate "Qualcomm IPQ8064 pin controller driver"
depends on GPIOLIB && OF

1
drivers/pinctrl/qcom/Makefile
View File

@ -1,6 +1,7 @@
# Qualcomm pin control drivers
obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o

9
drivers/pinctrl/qcom/pinctrl-apq8064.c
View File

@ -258,6 +258,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
@ -283,6 +284,7 @@ static const unsigned int sdc3_data_pins[] = { 95 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \
@ -324,6 +326,7 @@ enum apq8064_functions {
APQ_MUX_tsif1,
APQ_MUX_tsif2,
APQ_MUX_usb2_hsic,
APQ_MUX_ps_hold,
APQ_MUX_NA,
};
@ -351,6 +354,9 @@ static const char * const gpio_groups[] = {
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
};
static const char * const ps_hold_groups[] = {
"gpio78"
};
static const char * const gsbi1_groups[] = {
"gpio18", "gpio19", "gpio20", "gpio21"
};
@ -477,6 +483,7 @@ static const struct msm_function apq8064_functions[] = {
FUNCTION(tsif1),
FUNCTION(tsif2),
FUNCTION(usb2_hsic),
FUNCTION(ps_hold),
};
static const struct msm_pingroup apq8064_groups[] = {
@ -558,7 +565,7 @@ static const struct msm_pingroup apq8064_groups[] = {
PINGROUP(75, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(76, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(77, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(78, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(78, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(79, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(80, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(81, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),

1245
drivers/pinctrl/qcom/pinctrl-apq8084.c 100644
View File

File diff suppressed because it is too large Load Diff

2
drivers/pinctrl/qcom/pinctrl-ipq8064.c
View File

@ -211,6 +211,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
@ -236,6 +237,7 @@ static const unsigned int sdc3_data_pins[] = { 71 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \

49
drivers/pinctrl/qcom/pinctrl-msm.c
View File

@ -12,6 +12,7 @@
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
@ -26,6 +27,7 @@
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/reboot.h>
#include "../core.h"
#include "../pinconf.h"
@ -33,12 +35,14 @@
#include "../pinctrl-utils.h"
#define MAX_NR_GPIO 300
#define PS_HOLD_OFFSET 0x820
/**
* struct msm_pinctrl - state for a pinctrl-msm device
* @dev: device handle.
* @pctrl: pinctrl handle.
* @chip: gpiochip handle.
* @restart_nb: restart notifier block.
* @irq: parent irq for the TLMM irq_chip.
* @lock: Spinlock to protect register resources as well
* as msm_pinctrl data structures.
@ -52,6 +56,7 @@ struct msm_pinctrl {
struct device *dev;
struct pinctrl_dev *pctrl;
struct gpio_chip chip;
struct notifier_block restart_nb;
int irq;
spinlock_t lock;
@ -130,9 +135,9 @@ static int msm_get_function_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct msm_pingroup *g;
@ -166,7 +171,7 @@ static const struct pinmux_ops msm_pinmux_ops = {
.get_functions_count = msm_get_functions_count,
.get_function_name = msm_get_function_name,
.get_function_groups = msm_get_function_groups,
.enable = msm_pinmux_enable,
.set_mux = msm_pinmux_set_mux,
};
static int msm_config_reg(struct msm_pinctrl *pctrl,
@ -649,8 +654,6 @@ static void msm_gpio_irq_ack(struct irq_data *d)
spin_unlock_irqrestore(&pctrl->lock, flags);
}
#define INTR_TARGET_PROC_APPS 4
static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
@ -674,7 +677,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
/* Route interrupts to application cpu */
val = readl(pctrl->regs + g->intr_target_reg);
val &= ~(7 << g->intr_target_bit);
val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
val |= g->intr_target_kpss_val << g->intr_target_bit;
writel(val, pctrl->regs + g->intr_target_reg);
/* Update configuration for gpio.
@ -829,6 +832,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
if (ret) {
dev_err(pctrl->dev, "Failed to add pin range\n");
gpiochip_remove(&pctrl->chip);
return ret;
}
@ -839,6 +843,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
IRQ_TYPE_NONE);
if (ret) {
dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n");
gpiochip_remove(&pctrl->chip);
return -ENOSYS;
}
@ -848,6 +853,32 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
return 0;
}
static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
void *data)
{
struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
writel(0, pctrl->regs + PS_HOLD_OFFSET);
mdelay(1000);
return NOTIFY_DONE;
}
static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
{
int i = 0;
const struct msm_function *func = pctrl->soc->functions;
for (; i <= pctrl->soc->nfunctions; i++)
if (!strcmp(func[i].name, "ps_hold")) {
pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
pctrl->restart_nb.priority = 128;
if (register_restart_handler(&pctrl->restart_nb))
dev_err(pctrl->dev,
"failed to setup restart handler.\n");
break;
}
}
int msm_pinctrl_probe(struct platform_device *pdev,
const struct msm_pinctrl_soc_data *soc_data)
{
@ -871,6 +902,8 @@ int msm_pinctrl_probe(struct platform_device *pdev,
if (IS_ERR(pctrl->regs))
return PTR_ERR(pctrl->regs);
msm_pinctrl_setup_pm_reset(pctrl);
pctrl->irq = platform_get_irq(pdev, 0);
if (pctrl->irq < 0) {
dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
@ -913,6 +946,8 @@ int msm_pinctrl_remove(struct platform_device *pdev)
pinctrl_unregister(pctrl->pctrl);
unregister_restart_handler(&pctrl->restart_nb);
return 0;
}
EXPORT_SYMBOL(msm_pinctrl_remove);

3
drivers/pinctrl/qcom/pinctrl-msm.h
View File

@ -53,6 +53,8 @@ struct msm_function {
* @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
* status.
* @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
* @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
* this gpio should get routed to the KPSS processor.
* @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
* @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
* @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
@ -88,6 +90,7 @@ struct msm_pingroup {
unsigned intr_ack_high:1;
unsigned intr_target_bit:5;
unsigned intr_target_kpss_val:5;
unsigned intr_raw_status_bit:5;
unsigned intr_polarity_bit:5;
unsigned intr_detection_bit:5;

2
drivers/pinctrl/qcom/pinctrl-msm8960.c
View File

@ -384,6 +384,7 @@ static const unsigned int sdc3_data_pins[] = { 157 };
.intr_status_bit = 0, \
.intr_ack_high = 1, \
.intr_target_bit = 0, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 3, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
@ -409,6 +410,7 @@ static const unsigned int sdc3_data_pins[] = { 157 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \

2
drivers/pinctrl/qcom/pinctrl-msm8x74.c
View File

@ -366,6 +366,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
.intr_enable_bit = 0, \
.intr_status_bit = 0, \
.intr_target_bit = 5, \
.intr_target_kpss_val = 4, \
.intr_raw_status_bit = 4, \
.intr_polarity_bit = 1, \
.intr_detection_bit = 2, \
@ -391,6 +392,7 @@ static const unsigned int sdc2_data_pins[] = { 151 };
.intr_enable_bit = -1, \
.intr_status_bit = -1, \
.intr_target_bit = -1, \
.intr_target_kpss_val = -1, \
.intr_raw_status_bit = -1, \
.intr_polarity_bit = -1, \
.intr_detection_bit = -1, \

7
drivers/pinctrl/samsung/pinctrl-exynos5440.c
View File

@ -364,8 +364,9 @@ static void exynos5440_pinmux_setup(struct pinctrl_dev *pctldev, unsigned select
}
/* enable a specified pinmux by writing to registers */
static int exynos5440_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int exynos5440_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned group)
{
exynos5440_pinmux_setup(pctldev, selector, group, true);
return 0;
@ -387,7 +388,7 @@ static const struct pinmux_ops exynos5440_pinmux_ops = {
.get_functions_count = exynos5440_get_functions_count,
.get_function_name = exynos5440_pinmux_get_fname,
.get_function_groups = exynos5440_pinmux_get_groups,
.enable = exynos5440_pinmux_enable,
.set_mux = exynos5440_pinmux_set_mux,
.gpio_set_direction = exynos5440_pinmux_gpio_set_direction,
};

7
drivers/pinctrl/samsung/pinctrl-samsung.c
View File

@ -401,8 +401,9 @@ static void samsung_pinmux_setup(struct pinctrl_dev *pctldev, unsigned selector,
}
/* enable a specified pinmux by writing to registers */
static int samsung_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int samsung_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned group)
{
samsung_pinmux_setup(pctldev, selector, group, true);
return 0;
@ -413,7 +414,7 @@ static const struct pinmux_ops samsung_pinmux_ops = {
.get_functions_count = samsung_get_functions_count,
.get_function_name = samsung_pinmux_get_fname,
.get_function_groups = samsung_pinmux_get_groups,
.enable = samsung_pinmux_enable,
.set_mux = samsung_pinmux_set_mux,
};
/* set or get the pin config settings for a specified pin */

10
drivers/pinctrl/sh-pfc/core.c
View File

@ -542,7 +542,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
*/
ret = sh_pfc_register_pinctrl(pfc);
if (unlikely(ret != 0))
goto error;
return ret;
#ifdef CONFIG_GPIO_SH_PFC
/*
@ -564,11 +564,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
dev_info(pfc->dev, "%s support registered\n", info->name);
return 0;
error:
if (info->ops && info->ops->exit)
info->ops->exit(pfc);
return ret;
}
static int sh_pfc_remove(struct platform_device *pdev)
@ -580,9 +575,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
#endif
sh_pfc_unregister_pinctrl(pfc);
if (pfc->info->ops && pfc->info->ops->exit)
pfc->info->ops->exit(pfc);
return 0;
}

1
drivers/pinctrl/sh-pfc/core.h
View File

@ -33,7 +33,6 @@ struct sh_pfc_pin_range {
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
void *soc_data;
spinlock_t lock;
unsigned int num_windows;

4
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View File

@ -2717,14 +2717,14 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
iowrite8(value, addr);
}
static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
.get_bias = r8a73a4_pinmux_get_bias,
.set_bias = r8a73a4_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
.name = "r8a73a4_pfc",
.ops = &r8a73a4_pinmux_ops,
.ops = &r8a73a4_pfc_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },

4
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View File

@ -3752,14 +3752,14 @@ static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
iowrite8(value, addr);
}
static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
.get_bias = r8a7740_pinmux_get_bias,
.set_bias = r8a7740_pinmux_set_bias,
};
const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
.ops = &r8a7740_pinmux_ops,
.ops = &r8a7740_pfc_ops,
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },

4
drivers/pinctrl/sh-pfc/pfc-sh7372.c
View File

@ -2614,14 +2614,14 @@ static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
iowrite8(value, addr);
}
static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
static const struct sh_pfc_soc_operations sh7372_pfc_ops = {
.get_bias = sh7372_pinmux_get_bias,
.set_bias = sh7372_pinmux_set_bias,
};
const struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
.ops = &sh7372_pinmux_ops,
.ops = &sh7372_pfc_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },

23
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View File

@ -3824,39 +3824,28 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
* SoC information
*/
struct sh73a0_pinmux_data {
struct regulator_dev *vccq_mc0;
};
static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
{
struct sh73a0_pinmux_data *data;
struct regulator_config cfg = { };
struct regulator_dev *vccq;
int ret;
data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
if (data == NULL)
return -ENOMEM;
cfg.dev = pfc->dev;
cfg.init_data = &sh73a0_vccq_mc0_init_data;
cfg.driver_data = pfc;
data->vccq_mc0 = devm_regulator_register(pfc->dev,
&sh73a0_vccq_mc0_desc, &cfg);
if (IS_ERR(data->vccq_mc0)) {
ret = PTR_ERR(data->vccq_mc0);
vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
if (IS_ERR(vccq)) {
ret = PTR_ERR(vccq);
dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
ret);
return ret;
}
pfc->soc_data = data;
return 0;
}
static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
.init = sh73a0_pinmux_soc_init,
.get_bias = sh73a0_pinmux_get_bias,
.set_bias = sh73a0_pinmux_set_bias,
@ -3864,7 +3853,7 @@ static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.name = "sh73a0_pfc",
.ops = &sh73a0_pinmux_ops,
.ops = &sh73a0_pfc_ops,
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },

6
drivers/pinctrl/sh-pfc/pinctrl.c
View File

@ -312,8 +312,8 @@ static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
return 0;
}
static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
struct sh_pfc *pfc = pmx->pfc;
@ -442,7 +442,7 @@ static const struct pinmux_ops sh_pfc_pinmux_ops = {
.get_functions_count = sh_pfc_get_functions_count,
.get_function_name = sh_pfc_get_function_name,
.get_function_groups = sh_pfc_get_function_groups,
.enable = sh_pfc_func_enable,
.set_mux = sh_pfc_func_set_mux,
.gpio_request_enable = sh_pfc_gpio_request_enable,
.gpio_disable_free = sh_pfc_gpio_disable_free,
.gpio_set_direction = sh_pfc_gpio_set_direction,

1
drivers/pinctrl/sh-pfc/sh_pfc.h
View File

@ -116,7 +116,6 @@ struct sh_pfc;
struct sh_pfc_soc_operations {
int (*init)(struct sh_pfc *pfc);
void (*exit)(struct sh_pfc *pfc);
unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
unsigned int bias);

129
drivers/pinctrl/sirf/pinctrl-atlas6.c
View File

@ -134,8 +134,9 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
.mask = BIT(30) | BIT(31),
}, {
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
},
};
@ -148,14 +149,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = {
.funcval = 0,
};
static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
84, 85, 86, 95 };
static const unsigned lcd_16bits_pins[] = { 62, 63, 65, 70, 71, 72, 73, 74, 75,
76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
{
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
@ -174,21 +176,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = {
.funcval = 0,
};
static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
84, 85, 86, 95 };
static const unsigned lcd_18bits_pins[] = { 16, 17, 62, 63, 65, 70, 71, 72, 73,
74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95 };
static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
{
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(15) |
BIT(16) | BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
.mask = BIT(30) | BIT(31),
}, {
.group = 0,
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
BIT(21) | BIT(22) | BIT(23),
},
};
@ -200,14 +204,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = {
.funcval = 0,
};
static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79,
80, 81, 82, 83, 84, 85, 86, 95};
static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 62,
63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84,
85, 86, 95};
static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
{
.group = 2,
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) |
.mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
BIT(11) | BIT(12) | BIT(13) | BIT(15) | BIT(16) |
BIT(17) | BIT(18) | BIT(19) |
BIT(20) | BIT(21) | BIT(22) | BIT(31),
}, {
.group = 1,
@ -226,8 +232,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = {
.funcval = BIT(4),
};
static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83,
84, 85, 86, 95};
static const unsigned lcdrom_pins[] = { 8, 62, 63, 65, 70, 71, 72, 73, 74, 75,
76, 77, 79, 80, 81, 82, 83, 84, 85, 86, 95};
static const struct sirfsoc_muxmask uart0_muxmask[] = {
{
@ -371,11 +377,42 @@ static const struct sirfsoc_padmux cko1_padmux = {
static const unsigned cko1_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_muxmask[] = {
static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
}, {
},
};
static const struct sirfsoc_padmux i2s_mclk_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
.muxmask = i2s_mclk_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const unsigned i2s_mclk_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
{
.group = 1,
.mask = BIT(19),
},
};
static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
.muxmask = i2s_ext_clk_input_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(2),
.funcval = BIT(2),
};
static const unsigned i2s_ext_clk_input_pins[] = { 51 };
static const struct sirfsoc_muxmask i2s_muxmask[] = {
{
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
@ -385,17 +422,12 @@ static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
}, {
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4),
},
@ -405,17 +437,12 @@ static const struct sirfsoc_padmux i2s_no_din_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
{
.group = 1,
.mask = BIT(10) | BIT(20) | BIT(23),
}, {
.group = 3,
.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
},
@ -425,11 +452,11 @@ static const struct sirfsoc_padmux i2s_6chn_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(3) | BIT(9),
.funcval = BIT(1) | BIT(3) | BIT(9),
.funcmask = BIT(1) | BIT(9),
.funcval = BIT(1) | BIT(9),
};
static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
static const struct sirfsoc_muxmask ac97_muxmask[] = {
{
@ -716,7 +743,8 @@ static const struct sirfsoc_padmux vip_padmux = {
.funcval = BIT(18),
};
static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59, 60, 61 };
static const unsigned vip_pins[] = { 36, 37, 38, 40, 41, 56, 57, 58, 59,
60, 61 };
static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
{
@ -737,7 +765,8 @@ static const struct sirfsoc_padmux vip_noupli_padmux = {
.funcval = BIT(15),
};
static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 87, 88, 89 };
static const unsigned vip_noupli_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
87, 88, 89 };
static const struct sirfsoc_muxmask i2c0_muxmask[] = {
{
@ -876,7 +905,8 @@ static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
.funcval = 0,
};
static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40, 41, 56, 57, 58, 59, 60, 61 };
static const unsigned usb0_upli_drvbus_pins[] = { 36, 37, 38, 39, 40,
41, 56, 57, 58, 59, 60, 61 };
static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
{
@ -968,6 +998,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
@ -1017,8 +1049,11 @@ static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const
uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2smclkgrp[] = { "i2smclkgrp" };
static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
@ -1038,7 +1073,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp,
@ -1068,12 +1104,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc2_nowp",
sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus",
usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
i2s_ext_clk_input_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),

173
drivers/pinctrl/sirf/pinctrl-prima2.c
View File

@ -135,8 +135,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
@ -152,14 +153,15 @@ static const struct sirfsoc_padmux lcd_16bits_padmux = {
.funcval = 0,
};
static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
@ -178,21 +180,23 @@ static const struct sirfsoc_padmux lcd_18bits_padmux = {
.funcval = 0,
};
static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
.mask = BIT(31),
}, {
.group = 0,
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
.mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
BIT(21) | BIT(22) | BIT(23),
},
};
@ -204,14 +208,16 @@ static const struct sirfsoc_padmux lcd_24bits_padmux = {
.funcval = 0,
};
static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
{
.group = 3,
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
.mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
BIT(17) | BIT(18),
}, {
.group = 2,
@ -230,8 +236,8 @@ static const struct sirfsoc_padmux lcdrom_padmux = {
.funcval = BIT(4),
};
static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
static const struct sirfsoc_muxmask uart0_muxmask[] = {
{
@ -380,12 +386,44 @@ static const struct sirfsoc_padmux cko1_padmux = {
static const unsigned cko1_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
{
.group = 1,
.mask = BIT(10),
},
};
static const struct sirfsoc_padmux i2s_mclk_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
.muxmask = i2s_mclk_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3),
.funcval = BIT(3),
};
static const unsigned i2s_mclk_pins[] = { 42 };
static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
{
.group = 1,
.mask = BIT(19),
},
};
static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
.muxmask = i2s_ext_clk_input_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(2),
.funcval = BIT(2),
};
static const unsigned i2s_ext_clk_input_pins[] = { 51 };
static const struct sirfsoc_muxmask i2s_muxmask[] = {
{
.group = 1,
.mask =
BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
| BIT(23) | BIT(28),
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
},
};
@ -393,11 +431,42 @@ static const struct sirfsoc_padmux i2s_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
.muxmask = i2s_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(3) | BIT(9),
.funcval = BIT(3),
};
static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(14),
},
};
static const struct sirfsoc_padmux i2s_no_din_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
.muxmask = i2s_no_din_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
};
static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
{
.group = 1,
.mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
| BIT(23) | BIT(28),
},
};
static const struct sirfsoc_padmux i2s_6chn_padmux = {
.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
.muxmask = i2s_6chn_muxmask,
.ctrlreg = SIRFSOC_RSC_PIN_MUX,
.funcmask = BIT(1) | BIT(9),
.funcval = BIT(1) | BIT(9),
};
static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
static const struct sirfsoc_muxmask ac97_muxmask[] = {
{
@ -685,7 +754,8 @@ static const struct sirfsoc_padmux vip_padmux = {
.funcval = 0,
};
static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
88, 89 };
static const struct sirfsoc_muxmask i2c0_muxmask[] = {
{
@ -735,7 +805,8 @@ static const struct sirfsoc_padmux viprom_padmux = {
.funcval = BIT(0),
};
static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
87, 88, 89 };
static const struct sirfsoc_muxmask pwm0_muxmask[] = {
{
@ -918,7 +989,11 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
@ -936,16 +1011,19 @@ static const char * const uart1grp[] = { "uart1grp" };
static const char * const uart2grp[] = { "uart2grp" };
static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
static const char * const usp0grp[] = { "usp0grp" };
static const char * const usp0_uart_nostreamctrl_grp[] =
{ "usp0_uart_nostreamctrl_grp" };
static const char * const usp0_uart_nostreamctrl_grp[] = {
"usp0_uart_nostreamctrl_grp"
};
static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
static const char * const usp1grp[] = { "usp1grp" };
static const char * const usp1_uart_nostreamctrl_grp[] =
{ "usp1_uart_nostreamctrl_grp" };
static const char * const usp1_uart_nostreamctrl_grp[] = {
"usp1_uart_nostreamctrl_grp"
};
static const char * const usp2grp[] = { "usp2grp" };
static const char * const usp2_uart_nostreamctrl_grp[] =
{ "usp2_uart_nostreamctrl_grp" };
static const char * const usp2_uart_nostreamctrl_grp[] = {
"usp2_uart_nostreamctrl_grp"
};
static const char * const i2c0grp[] = { "i2c0grp" };
static const char * const i2c1grp[] = { "i2c1grp" };
static const char * const pwm0grp[] = { "pwm0grp" };
@ -966,9 +1044,14 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" };
static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const
uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
static const char * const pulse_countgrp[] = { "pulse_countgrp" };
static const char * const i2smclkgrp[] = { "i2smclkgrp" };
static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
static const char * const i2sgrp[] = { "i2sgrp" };
static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
static const char * const ac97grp[] = { "ac97grp" };
static const char * const nandgrp[] = { "nandgrp" };
static const char * const spi0grp[] = { "spi0grp" };
@ -981,15 +1064,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
usp0_only_utfs_grp, usp0_only_utfs_padmux),
SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
usp0_only_urfs_grp, usp0_only_urfs_padmux),
SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
@ -1013,12 +1100,20 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
i2s_ext_clk_input_padmux),
SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),

72
drivers/pinctrl/sirf/pinctrl-sirf.c
View File

@ -58,17 +58,18 @@ static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
return sirfsoc_pin_groups[selector].name;
}
static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
const unsigned **pins,
unsigned *num_pins)
static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins)
{
*pins = sirfsoc_pin_groups[selector].pins;
*num_pins = sirfsoc_pin_groups[selector].num_pins;
return 0;
}
static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
unsigned offset)
static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned offset)
{
seq_printf(s, " " DRIVER_NAME);
}
@ -138,22 +139,25 @@ static struct pinctrl_ops sirfsoc_pctrl_ops = {
static struct sirfsoc_pmx_func *sirfsoc_pmx_functions;
static int sirfsoc_pmxfunc_cnt;
static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
bool enable)
static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx,
unsigned selector, bool enable)
{
int i;
const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
const struct sirfsoc_padmux *mux =
sirfsoc_pmx_functions[selector].padmux;
const struct sirfsoc_muxmask *mask = mux->muxmask;
for (i = 0; i < mux->muxmask_counts; i++) {
u32 muxval;
if (!spmx->is_marco) {
muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
muxval = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(mask[i].group));
if (enable)
muxval = muxval & ~mask[i].mask;
else
muxval = muxval | mask[i].mask;
writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
writel(muxval, spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(mask[i].group));
} else {
if (enable)
writel(mask[i].mask, spmx->gpio_virtbase +
@ -175,8 +179,9 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector
}
}
static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
unsigned group)
static int sirfsoc_pinmux_set_mux(struct pinctrl_dev *pmxdev,
unsigned selector,
unsigned group)
{
struct sirfsoc_pmx *spmx;
@ -197,9 +202,10 @@ static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
return sirfsoc_pmx_functions[selector].name;
}
static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
const char * const **groups,
unsigned * const num_groups)
static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev,
unsigned selector,
const char * const **groups,
unsigned * const num_groups)
{
*groups = sirfsoc_pmx_functions[selector].groups;
*num_groups = sirfsoc_pmx_functions[selector].num_groups;
@ -218,9 +224,11 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
spmx = pinctrl_dev_get_drvdata(pmxdev);
if (!spmx->is_marco) {
muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
muxval = readl(spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(group));
muxval = muxval | (1 << (offset - range->pin_base));
writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
writel(muxval, spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(group));
} else {
writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
SIRFSOC_GPIO_PAD_EN(group));
@ -230,7 +238,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
}
static struct pinmux_ops sirfsoc_pinmux_ops = {
.enable = sirfsoc_pinmux_enable,
.set_mux = sirfsoc_pinmux_set_mux,
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
.get_function_name = sirfsoc_pinmux_get_func_name,
.get_function_groups = sirfsoc_pinmux_get_groups,
@ -518,24 +526,29 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
case IRQ_TYPE_NONE:
break;
case IRQ_TYPE_EDGE_RISING:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
break;
case IRQ_TYPE_EDGE_FALLING:
val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
break;
case IRQ_TYPE_EDGE_BOTH:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
break;
case IRQ_TYPE_LEVEL_LOW:
val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
break;
case IRQ_TYPE_LEVEL_HIGH:
val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
break;
}
@ -694,7 +707,8 @@ static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_chip *sgpio,
spin_unlock_irqrestore(&bank->lock, flags);
}
static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
unsigned gpio, int value)
{
struct sirfsoc_gpio_chip *sgpio = to_sirfsoc_gpio(chip);
struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, gpio);
@ -839,7 +853,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
if (err) {
dev_err(&pdev->dev,
"could not connect irqchip to gpiochip\n");
goto out;
goto out_banks;
}
for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
@ -898,8 +912,8 @@ static int __init sirfsoc_gpio_init(void)
}
subsys_initcall(sirfsoc_gpio_init);
MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
"Yuping Luo <yuping.luo@csr.com>, "
"Barry Song <baohua.song@csr.com>");
MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
MODULE_AUTHOR("Yuping Luo <yuping.luo@csr.com>");
MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
MODULE_DESCRIPTION("SIRFSOC pin control driver");
MODULE_LICENSE("GPL");

4
drivers/pinctrl/spear/pinctrl-spear.c
View File

@ -268,7 +268,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
return 0;
}
static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
unsigned group)
{
return spear_pinctrl_endisable(pctldev, function, group, true);
@ -338,7 +338,7 @@ static const struct pinmux_ops spear_pinmux_ops = {
.get_functions_count = spear_pinctrl_get_funcs_count,
.get_function_name = spear_pinctrl_get_func_name,
.get_function_groups = spear_pinctrl_get_func_groups,
.enable = spear_pinctrl_enable,
.set_mux = spear_pinctrl_set_mux,
.gpio_request_enable = gpio_request_enable,
.gpio_disable_free = gpio_disable_free,
};

2
drivers/pinctrl/spear/pinctrl-spear1310.c
View File

@ -2692,7 +2692,7 @@ static struct spear_pinctrl_machdata spear1310_machdata = {
.modes_supported = false,
};
static struct of_device_id spear1310_pinctrl_of_match[] = {
static const struct of_device_id spear1310_pinctrl_of_match[] = {
{
.compatible = "st,spear1310-pinmux",
},

2
drivers/pinctrl/spear/pinctrl-spear1340.c
View File

@ -2008,7 +2008,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = {
.modes_supported = false,
};
static struct of_device_id spear1340_pinctrl_of_match[] = {
static const struct of_device_id spear1340_pinctrl_of_match[] = {
{
.compatible = "st,spear1340-pinmux",
},

2
drivers/pinctrl/spear/pinctrl-spear300.c
View File

@ -646,7 +646,7 @@ static struct spear_function *spear300_functions[] = {
&gpio1_function,
};
static struct of_device_id spear300_pinctrl_of_match[] = {
static const struct of_device_id spear300_pinctrl_of_match[] = {
{
.compatible = "st,spear300-pinmux",
},

2
drivers/pinctrl/spear/pinctrl-spear310.c
View File

@ -371,7 +371,7 @@ static struct spear_function *spear310_functions[] = {
&tdm_function,
};
static struct of_device_id spear310_pinctrl_of_match[] = {
static const struct of_device_id spear310_pinctrl_of_match[] = {
{
.compatible = "st,spear310-pinmux",
},

2
drivers/pinctrl/spear/pinctrl-spear320.c
View File

@ -3410,7 +3410,7 @@ static struct spear_function *spear320_functions[] = {
&i2c2_function,
};
static struct of_device_id spear320_pinctrl_of_match[] = {
static const struct of_device_id spear320_pinctrl_of_match[] = {
{
.compatible = "st,spear320-pinmux",
},

8
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -393,9 +393,9 @@ static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
spin_unlock_irqrestore(&pctl->lock, flags);
}
static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
{
struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
struct sunxi_pinctrl_group *g = pctl->groups + group;
@ -441,7 +441,7 @@ static const struct pinmux_ops sunxi_pmx_ops = {
.get_functions_count = sunxi_pmx_get_funcs_cnt,
.get_function_name = sunxi_pmx_get_func_name,
.get_function_groups = sunxi_pmx_get_func_groups,
.enable = sunxi_pmx_enable,
.set_mux = sunxi_pmx_set_mux,
.gpio_set_direction = sunxi_pmx_gpio_set_direction,
};

8
drivers/pinctrl/vt8500/pinctrl-wmt.c
View File

@ -131,9 +131,9 @@ static int wmt_set_pinmux(struct wmt_pinctrl_data *data, unsigned func,
return 0;
}
static int wmt_pmx_enable(struct pinctrl_dev *pctldev,
unsigned func_selector,
unsigned group_selector)
static int wmt_pmx_set_mux(struct pinctrl_dev *pctldev,
unsigned func_selector,
unsigned group_selector)
{
struct wmt_pinctrl_data *data = pinctrl_dev_get_drvdata(pctldev);
u32 pinnum = data->pins[group_selector].number;
@ -168,7 +168,7 @@ static struct pinmux_ops wmt_pinmux_ops = {
.get_functions_count = wmt_pmx_get_functions_count,
.get_function_name = wmt_pmx_get_function_name,
.get_function_groups = wmt_pmx_get_function_groups,
.enable = wmt_pmx_enable,
.set_mux = wmt_pmx_set_mux,
.gpio_disable_free = wmt_pmx_gpio_disable_free,
.gpio_set_direction = wmt_pmx_gpio_set_direction,
};

5
include/dt-bindings/pinctrl/at91.h
View File

@ -20,6 +20,11 @@
#define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH)
#define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5)
#define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5)
#define AT91_PIOA 0
#define AT91_PIOB 1
#define AT91_PIOC 2

2
include/dt-bindings/pinctrl/rockchip.h
View File

@ -28,5 +28,7 @@
#define RK_FUNC_GPIO 0
#define RK_FUNC_1 1
#define RK_FUNC_2 2
#define RK_FUNC_3 3
#define RK_FUNC_4 4
#endif

2
include/linux/pinctrl/pinconf-generic.h
View File

@ -57,7 +57,7 @@
* which are then pulled up with an external resistor. Setting this
* config will enable open drain mode, the argument is ignored.
* @PIN_CONFIG_DRIVE_OPEN_SOURCE: the pin will be driven with open source
* (open emitter). Setting this config will enable open drain mode, the
* (open emitter). Setting this config will enable open source mode, the
* argument is ignored.
* @PIN_CONFIG_DRIVE_STRENGTH: the pin will sink or source at most the current
* passed as argument. The argument is in mA.

7
include/linux/pinctrl/pinmux.h
View File

@ -39,13 +39,12 @@ struct pinctrl_dev;
* name can be used with the generic @pinctrl_ops to retrieve the
* actual pins affected. The applicable groups will be returned in
* @groups and the number of groups in @num_groups
* @enable: enable a certain muxing function with a certain pin group. The
* @set_mux: enable a certain muxing function with a certain pin group. The
* driver does not need to figure out whether enabling this function
* conflicts some other use of the pins in that group, such collisions
* are handled by the pinmux subsystem. The @func_selector selects a
* certain function whereas @group_selector selects a certain set of pins
* to be used. On simple controllers the latter argument may be ignored
* @disable: disable a certain muxing selector with a certain pin group
* @gpio_request_enable: requests and enables GPIO on a certain pin.
* Implement this only if you can mux every pin individually as GPIO. The
* affected GPIO range is passed along with an offset(pin number) into that
@ -68,8 +67,8 @@ struct pinmux_ops {
unsigned selector,
const char * const **groups,
unsigned * const num_groups);
int (*enable) (struct pinctrl_dev *pctldev, unsigned func_selector,
unsigned group_selector);
int (*set_mux) (struct pinctrl_dev *pctldev, unsigned func_selector,
unsigned group_selector);
int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset);