MLK-11479-04 ASoC: imx-wm8962: Set MCLK source clock to 0Hz in hw_free()
cherry-pick below patch from v3.14.y: ENGR00274386-2 ASoC: imx-wm8962: Set MCLK source clock to 0Hz in hw_free() When DAPM closed WM8962 after playback, its driver would prompt 'wm8962 0-001a: Unsupported sysclk ratio 500' due to the invalid divisor calculated by WM8962 codec driver. To fix it, we can work around by setting its MCLK source to 0Hz, so the codec driver would never get an invalid divisor any more. Since hw_params() would re-set the MCLK source, no need to worry about any side-effect. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com> (cherry picked from commit a935f7680ac3958ce72cf7413cac278c0683d4c0)
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@ -129,7 +129,7 @@ static int imx_hifi_hw_free(struct snd_pcm_substream *substream)
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* So we set MCLK as sysclk once, which'd remove the limitation.
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*/
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ret = snd_soc_dai_set_sysclk(codec_dai, WM8962_SYSCLK_MCLK,
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data->clk_frequency, SND_SOC_CLOCK_IN);
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0, SND_SOC_CLOCK_IN);
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if (ret < 0) {
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dev_err(dev, "failed to switch away from FLL: %d\n", ret);
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return ret;
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