mv643xx_eth: Check ETH_INT_CAUSE_STATE bit
Commit 468d09f894
masked the "state"
interrupt (bit 20 of the cause register). This results in Radstone's
PPC7D repeatedly re-entering the interrupt routine, locking up the
board. The following patch returns the required handling for this
interrupt.
Signed-off-by: Martyn Welch <martyn.welch@radstone.co.uk>
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -534,7 +534,7 @@ static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
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}
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/* PHY status changed */
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if (eth_int_cause_ext & ETH_INT_CAUSE_PHY) {
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if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
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struct ethtool_cmd cmd;
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if (mii_link_ok(&mp->mii)) {
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@ -64,7 +64,9 @@
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#define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
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#define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
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#define ETH_INT_CAUSE_PHY 0x00010000
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#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
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#define ETH_INT_CAUSE_STATE 0x00100000
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#define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
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ETH_INT_CAUSE_STATE)
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#define ETH_INT_MASK_ALL 0x00000000
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#define ETH_INT_MASK_ALL_EXT 0x00000000
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