drm/etnaviv: need to disable clock gating when doing profiling
As done by Vivante kernel driver. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -1346,6 +1346,13 @@ static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
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static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
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struct etnaviv_event *event)
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{
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u32 val;
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/* disable clock gating */
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val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
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val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
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gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
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sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
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}
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@ -1354,6 +1361,7 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
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{
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const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf;
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unsigned int i;
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u32 val;
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sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
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@ -1362,6 +1370,11 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
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*pmr->bo_vma = pmr->sequence;
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}
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/* enable clock gating */
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val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
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val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
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gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
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}
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