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clk: samsung: exynos7: Adds missing clocks gates of CMU_TOPC

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This adds some of the missing GATE clocks of CMU_TOPC block.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Alim Akhtar 2015-09-10 14:14:27 +05:30 committed by Sylwester Nawrocki
parent dc504b2277
commit 2cbb515745
2 changed files with 39 additions and 1 deletions
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27
drivers/clk/samsung/clk-exynos7.c
View file

@ -32,7 +32,9 @@
#define DIV_TOPC0 0x0600
#define DIV_TOPC1 0x0604
#define DIV_TOPC3 0x060C
#define ENABLE_ACLK_TOPC0 0x0800
#define ENABLE_ACLK_TOPC1 0x0804
#define ENABLE_SCLK_TOPC1 0x0A04
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
@ -143,8 +145,33 @@ static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
};
static struct samsung_gate_clock topc_gate_clks[] __initdata = {
GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
ENABLE_ACLK_TOPC0, 4, 0, 0),
GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
ENABLE_ACLK_TOPC1, 20, 0, 0),
GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
ENABLE_ACLK_TOPC1, 24, 0, 0),
GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
ENABLE_SCLK_TOPC1, 20, 0, 0),
GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
ENABLE_SCLK_TOPC1, 17, 0, 0),
GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
ENABLE_SCLK_TOPC1, 16, 0, 0),
GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
ENABLE_SCLK_TOPC1, 13, 0, 0),
GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
ENABLE_SCLK_TOPC1, 12, 0, 0),
GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
ENABLE_SCLK_TOPC1, 5, 0, 0),
GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
ENABLE_SCLK_TOPC1, 4, 0, 0),
GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
ENABLE_SCLK_TOPC1, 1, 0, 0),
GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
ENABLE_SCLK_TOPC1, 0, 0, 0),
};
static struct samsung_pll_clock topc_pll_clks[] __initdata = {

13
include/dt-bindings/clock/exynos7-clk.h
View file

@ -21,7 +21,18 @@
#define ACLK_MSCL_532 8
#define DOUT_SCLK_AUD_PLL 9
#define FOUT_AUD_PLL 10
#define TOPC_NR_CLK 11
#define SCLK_AUD_PLL 11
#define SCLK_MFC_PLL_B 12
#define SCLK_MFC_PLL_A 13
#define SCLK_BUS1_PLL_B 14
#define SCLK_BUS1_PLL_A 15
#define SCLK_BUS0_PLL_B 16
#define SCLK_BUS0_PLL_A 17
#define SCLK_CC_PLL_B 18
#define SCLK_CC_PLL_A 19
#define ACLK_CCORE_133 20
#define ACLK_PERIS_66 21
#define TOPC_NR_CLK 22
/* TOP0 */
#define DOUT_ACLK_PERIC1 1