MIPS: TXx9: Modernize printing of kernel messages
- Convert from printk() to pr_*(),
- Add missing continuations, to fix user-visible breakage,
- Drop superfluous casts (u64 has been unsigned long long on all
architectures for many years).
On rbtx4927, this restores the kernel output like:
-TX4927 SDRAMC --
- CR0:0000007e00000544
- TR:32800030e
+TX4927 SDRAMC -- CR0:0000007e00000544 TR:32800030e
and:
-PCIC -- PCICLK:
-Internal(33.3MHz)
-
+PCIC -- PCICLK:Internal(33.3MHz)
Fixes: 4bcc595ccd
("printk: reinstate KERN_CONT for printing continuation lines")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Reviewed-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/14646/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
2b58a76e2f
commit
2cec11d871
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@ -21,9 +21,9 @@ int __init tx4927_report_pciclk(void)
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{
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int pciclk = 0;
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printk(KERN_INFO "PCIC --%s PCICLK:",
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(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
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" PCI66" : "");
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pr_info("PCIC --%s PCICLK:",
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(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
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" PCI66" : "");
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if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
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u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
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switch ((unsigned long)ccfg &
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@ -37,14 +37,14 @@ int __init tx4927_report_pciclk(void)
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case TX4927_CCFG_PCIDIVMODE_6:
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pciclk = txx9_cpu_clock / 6; break;
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}
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printk("Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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pr_cont("Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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} else {
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printk("External");
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pr_cont("External");
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pciclk = -1;
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}
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printk("\n");
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pr_cont("\n");
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return pciclk;
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}
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@ -74,8 +74,8 @@ int __init tx4927_pciclk66_setup(void)
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}
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tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
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pcidivmode);
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printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
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(unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
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pr_debug("PCICLK: ccfg:%08lx\n",
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(unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
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} else
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pciclk = -1;
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return pciclk;
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@ -87,5 +87,5 @@ void __init tx4927_setup_pcierr_irq(void)
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tx4927_pcierr_interrupt,
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0, "PCI error",
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(void *)TX4927_PCIC_REG))
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printk(KERN_WARNING "Failed to request irq for PCIERR\n");
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pr_warn("Failed to request irq for PCIERR\n");
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}
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@ -21,9 +21,9 @@ int __init tx4938_report_pciclk(void)
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{
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int pciclk = 0;
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printk(KERN_INFO "PCIC --%s PCICLK:",
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(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
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" PCI66" : "");
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pr_info("PCIC --%s PCICLK:",
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(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
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" PCI66" : "");
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if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
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u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
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switch ((unsigned long)ccfg &
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@ -45,14 +45,14 @@ int __init tx4938_report_pciclk(void)
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case TX4938_CCFG_PCIDIVMODE_11:
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pciclk = txx9_cpu_clock / 11; break;
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}
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printk("Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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pr_cont("Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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} else {
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printk("External");
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pr_cont("External");
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pciclk = -1;
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}
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printk("\n");
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pr_cont("\n");
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return pciclk;
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}
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@ -62,10 +62,10 @@ void __init tx4938_report_pci1clk(void)
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unsigned int pciclk =
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txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
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printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n",
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(ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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pr_info("PCIC1 -- %sPCICLK:%u.%uMHz\n",
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(ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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}
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int __init tx4938_pciclk66_setup(void)
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@ -105,8 +105,8 @@ int __init tx4938_pciclk66_setup(void)
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}
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tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
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pcidivmode);
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printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
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(unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
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pr_debug("PCICLK: ccfg:%08lx\n",
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(unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
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} else
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pciclk = -1;
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return pciclk;
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@ -138,5 +138,5 @@ void __init tx4938_setup_pcierr_irq(void)
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tx4927_pcierr_interrupt,
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0, "PCI error",
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(void *)TX4927_PCIC_REG))
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printk(KERN_WARNING "Failed to request irq for PCIERR\n");
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pr_warn("Failed to request irq for PCIERR\n");
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}
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@ -28,14 +28,14 @@ int __init tx4939_report_pciclk(void)
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pciclk = txx9_master_clock * 20 / 6;
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if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
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pciclk /= 2;
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printk(KERN_CONT "Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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pr_cont("Internal(%u.%uMHz)",
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(pciclk + 50000) / 1000000,
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((pciclk + 50000) / 100000) % 10);
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} else {
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printk(KERN_CONT "External");
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pr_cont("External");
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pciclk = -1;
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}
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printk(KERN_CONT "\n");
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pr_cont("\n");
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return pciclk;
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}
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@ -55,7 +55,7 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
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/* It seems SLC90E66 needs some time after PCI reset... */
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mdelay(80);
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printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
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pr_info("PCI: Checking 66MHz capabilities...\n");
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for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
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if (PCI_FUNC(pci_devfn))
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@ -74,9 +74,8 @@ int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
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early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_STATUS, &stat);
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if (!(stat & PCI_STATUS_66MHZ)) {
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printk(KERN_DEBUG
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"PCI: %02x:%02x not 66MHz capable.\n",
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current_bus, pci_devfn);
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pr_debug("PCI: %02x:%02x not 66MHz capable.\n",
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current_bus, pci_devfn);
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cap66 = 0;
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break;
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}
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@ -209,8 +208,8 @@ txx9_alloc_pci_controller(struct pci_controller *pcic,
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pcic->mem_offset = 0; /* busaddr == physaddr */
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printk(KERN_INFO "PCI: IO %pR MEM %pR\n",
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&pcic->mem_resource[1], &pcic->mem_resource[0]);
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pr_info("PCI: IO %pR MEM %pR\n", &pcic->mem_resource[1],
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&pcic->mem_resource[0]);
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/* register_pci_controller() will request MEM resource */
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release_resource(&pcic->mem_resource[0]);
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@ -219,7 +218,7 @@ txx9_alloc_pci_controller(struct pci_controller *pcic,
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release_resource(&pcic->mem_resource[0]);
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free_and_exit:
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kfree(new);
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printk(KERN_ERR "PCI: Failed to allocate resources.\n");
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pr_err("PCI: Failed to allocate resources.\n");
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return NULL;
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}
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@ -260,7 +259,7 @@ static int txx9_i8259_irq_setup(int irq)
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err = request_irq(irq, &i8259_interrupt, IRQF_SHARED,
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"cascade(i8259)", (void *)(long)irq);
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if (!err)
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printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
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pr_info("PCI-ISA bridge PIC (irq %d)\n", irq);
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return err;
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}
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@ -308,13 +307,13 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
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/* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
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pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
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printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
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pr_info("PCI: %s: IRQ %02x", pci_name(dev), dat);
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/* enable SMSC SLC90E66 IDE */
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for (i = 0; i < ARRAY_SIZE(regs); i++) {
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pci_read_config_byte(dev, regs[i], &dat);
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pci_write_config_byte(dev, regs[i], dat | 0x80);
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pci_read_config_byte(dev, regs[i], &dat);
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printk(KERN_CONT " IDETIM%d %02x", i, dat);
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pr_cont(" IDETIM%d %02x", i, dat);
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}
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pci_read_config_byte(dev, 0x5c, &dat);
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/*
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dat |= 0x01;
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pci_write_config_byte(dev, 0x5c, dat);
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pci_read_config_byte(dev, 0x5c, &dat);
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printk(KERN_CONT " REG5C %02x", dat);
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printk(KERN_CONT "\n");
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pr_cont(" REG5C %02x\n", dat);
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}
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#endif /* CONFIG_TOSHIBA_FPCIB0 */
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@ -352,7 +350,7 @@ static void final_fixup(struct pci_dev *dev)
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(bist & PCI_BIST_CAPABLE)) {
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unsigned long timeout;
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pci_set_power_state(dev, PCI_D0);
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printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
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pr_info("PCI: %s BIST...", pci_name(dev));
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pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
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timeout = jiffies + HZ * 2; /* timeout after 2 sec */
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do {
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@ -361,9 +359,9 @@ static void final_fixup(struct pci_dev *dev)
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break;
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} while (bist & PCI_BIST_START);
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if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
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printk(KERN_CONT "failed. (0x%x)\n", bist);
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pr_cont("failed. (0x%x)\n", bist);
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else
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printk(KERN_CONT "OK.\n");
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pr_cont("OK.\n");
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}
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}
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@ -67,9 +67,9 @@ void __init tx3927_setup(void)
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/* do reset on watchdog */
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tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
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printk(KERN_INFO "TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
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tx3927_ccfgptr->crir,
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tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
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pr_info("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
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tx3927_ccfgptr->crir, tx3927_ccfgptr->ccfg,
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tx3927_ccfgptr->pcfg);
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/* TMR */
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for (i = 0; i < TX3927_NR_TMR; i++)
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@ -183,15 +183,14 @@ void __init tx4927_setup(void)
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if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))
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txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);
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printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str,
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(cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4927_ccfgptr->crir),
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(unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));
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pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str, (cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4927_ccfgptr->crir),
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____raw_readq(&tx4927_ccfgptr->ccfg),
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____raw_readq(&tx4927_ccfgptr->pcfg));
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printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
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pr_info("%s SDRAMC --", txx9_pcode_str);
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for (i = 0; i < 4; i++) {
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__u64 cr = TX4927_SDRAMC_CR(i);
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unsigned long base, size;
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@ -199,15 +198,14 @@ void __init tx4927_setup(void)
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continue; /* disabled */
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base = (unsigned long)(cr >> 49) << 21;
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size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
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printk(" CR%d:%016llx", i, (unsigned long long)cr);
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pr_cont(" CR%d:%016llx", i, cr);
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tx4927_sdram_resource[i].name = "SDRAM";
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tx4927_sdram_resource[i].start = base;
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tx4927_sdram_resource[i].end = base + size - 1;
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tx4927_sdram_resource[i].flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4927_sdram_resource[i]);
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}
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printk(" TR:%09llx\n",
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(unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));
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pr_cont(" TR:%09llx\n", ____raw_readq(&tx4927_sdramcptr->tr));
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/* TMR */
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/* disable all timers */
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@ -196,15 +196,14 @@ void __init tx4938_setup(void)
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if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
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txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
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printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str,
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(cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4938_ccfgptr->crir),
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(unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
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(unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
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pr_info("%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
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txx9_pcode_str, (cpuclk + 500000) / 1000000,
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(txx9_master_clock + 500000) / 1000000,
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(__u32)____raw_readq(&tx4938_ccfgptr->crir),
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____raw_readq(&tx4938_ccfgptr->ccfg),
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____raw_readq(&tx4938_ccfgptr->pcfg));
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printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
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pr_info("%s SDRAMC --", txx9_pcode_str);
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for (i = 0; i < 4; i++) {
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__u64 cr = TX4938_SDRAMC_CR(i);
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unsigned long base, size;
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@ -212,15 +211,14 @@ void __init tx4938_setup(void)
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continue; /* disabled */
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base = (unsigned long)(cr >> 49) << 21;
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size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;
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printk(" CR%d:%016llx", i, (unsigned long long)cr);
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pr_cont(" CR%d:%016llx", i, cr);
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tx4938_sdram_resource[i].name = "SDRAM";
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tx4938_sdram_resource[i].start = base;
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tx4938_sdram_resource[i].end = base + size - 1;
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tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
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}
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printk(" TR:%09llx\n",
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(unsigned long long)____raw_readq(&tx4938_sdramcptr->tr));
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pr_cont(" TR:%09llx\n", ____raw_readq(&tx4938_sdramcptr->tr));
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/* SRAM */
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if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) {
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@ -254,20 +252,20 @@ void __init tx4938_setup(void)
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txx9_clear64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_PCIC1RST);
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} else {
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printk(KERN_INFO "%s: stop PCIC1\n", txx9_pcode_str);
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pr_info("%s: stop PCIC1\n", txx9_pcode_str);
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/* stop PCIC1 */
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txx9_set64(&tx4938_ccfgptr->clkctr,
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TX4938_CLKCTR_PCIC1CKD);
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}
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if (!(pcfg & TX4938_PCFG_ETH0_SEL)) {
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printk(KERN_INFO "%s: stop ETH0\n", txx9_pcode_str);
|
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pr_info("%s: stop ETH0\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH0RST);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH0CKD);
|
||||
}
|
||||
if (!(pcfg & TX4938_PCFG_ETH1_SEL)) {
|
||||
printk(KERN_INFO "%s: stop ETH1\n", txx9_pcode_str);
|
||||
pr_info("%s: stop ETH1\n", txx9_pcode_str);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
TX4938_CLKCTR_ETH1RST);
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr,
|
||||
|
|
|
@ -221,8 +221,8 @@ void __init tx4939_setup(void)
|
|||
(txx9_master_clock + 500000) / 1000000,
|
||||
(txx9_gbus_clock + 500000) / 1000000,
|
||||
(__u32)____raw_readq(&tx4939_ccfgptr->crir),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
|
||||
(unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
|
||||
____raw_readq(&tx4939_ccfgptr->ccfg),
|
||||
____raw_readq(&tx4939_ccfgptr->pcfg));
|
||||
|
||||
pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
|
||||
(__u32)____raw_readq(&tx4939_ddrcptr->winen));
|
||||
|
@ -230,7 +230,7 @@ void __init tx4939_setup(void)
|
|||
__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
|
||||
if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
|
||||
continue; /* disabled */
|
||||
printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
|
||||
pr_cont(" #%d:%016llx", i, win);
|
||||
tx4939_sdram_resource[i].name = "DDR SDRAM";
|
||||
tx4939_sdram_resource[i].start =
|
||||
(unsigned long)(win >> 48) << 20;
|
||||
|
@ -240,7 +240,7 @@ void __init tx4939_setup(void)
|
|||
tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
|
||||
request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
|
||||
}
|
||||
printk(KERN_CONT "\n");
|
||||
pr_cont("\n");
|
||||
|
||||
/* SRAM */
|
||||
if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
|
||||
|
|
|
@ -105,9 +105,8 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
|
|||
u8 chip_id;
|
||||
|
||||
if (g_smsc_fdc37m81x_base)
|
||||
printk(KERN_WARNING "%s: stepping on old base=0x%0*lx\n",
|
||||
__func__,
|
||||
field, g_smsc_fdc37m81x_base);
|
||||
pr_warn("%s: stepping on old base=0x%0*lx\n", __func__, field,
|
||||
g_smsc_fdc37m81x_base);
|
||||
|
||||
g_smsc_fdc37m81x_base = port;
|
||||
|
||||
|
@ -117,8 +116,7 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
|
|||
if (chip_id == SMSC_FDC37M81X_CHIP_ID)
|
||||
smsc_fdc37m81x_config_end();
|
||||
else {
|
||||
printk(KERN_WARNING "%s: unknown chip id 0x%02x\n", __func__,
|
||||
chip_id);
|
||||
pr_warn("%s: unknown chip id 0x%02x\n", __func__, chip_id);
|
||||
g_smsc_fdc37m81x_base = 0;
|
||||
}
|
||||
|
||||
|
@ -128,9 +126,8 @@ unsigned long __init smsc_fdc37m81x_init(unsigned long port)
|
|||
#ifdef DEBUG
|
||||
static void smsc_fdc37m81x_config_dump_one(const char *key, u8 dev, u8 reg)
|
||||
{
|
||||
printk(KERN_INFO "%s: dev=0x%02x reg=0x%02x val=0x%02x\n",
|
||||
key, dev, reg,
|
||||
smsc_fdc37m81x_rd(reg));
|
||||
pr_info("%s: dev=0x%02x reg=0x%02x val=0x%02x\n", key, dev, reg,
|
||||
smsc_fdc37m81x_rd(reg));
|
||||
}
|
||||
|
||||
void smsc_fdc37m81x_config_dump(void)
|
||||
|
@ -142,7 +139,7 @@ void smsc_fdc37m81x_config_dump(void)
|
|||
|
||||
orig = smsc_fdc37m81x_rd(SMSC_FDC37M81X_DNUM);
|
||||
|
||||
printk(KERN_INFO "%s: common\n", fname);
|
||||
pr_info("%s: common\n", fname);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_DNUM);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
|
@ -154,7 +151,7 @@ void smsc_fdc37m81x_config_dump(void)
|
|||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_NONE,
|
||||
SMSC_FDC37M81X_PMGT);
|
||||
|
||||
printk(KERN_INFO "%s: keyboard\n", fname);
|
||||
pr_info("%s: keyboard\n", fname);
|
||||
smsc_dc37m81x_wr(SMSC_FDC37M81X_DNUM, SMSC_FDC37M81X_KBD);
|
||||
smsc_fdc37m81x_config_dump_one(fname, SMSC_FDC37M81X_KBD,
|
||||
SMSC_FDC37M81X_ACTIVE);
|
||||
|
|
|
@ -45,7 +45,7 @@ void __init jmr3927_prom_init(void)
|
|||
{
|
||||
/* CCFG */
|
||||
if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
|
||||
printk(KERN_ERR "TX3927 TLB off\n");
|
||||
pr_err("TX3927 TLB off\n");
|
||||
|
||||
add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
|
||||
txx9_sio_putchar_init(TX3927_SIO_REG(1));
|
||||
|
|
|
@ -150,12 +150,11 @@ static void __init jmr3927_board_init(void)
|
|||
|
||||
jmr3927_led_set(0);
|
||||
|
||||
printk(KERN_INFO
|
||||
"JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
|
||||
jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_dipsw1(), jmr3927_dipsw2(),
|
||||
jmr3927_dipsw3(), jmr3927_dipsw4());
|
||||
pr_info("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
|
||||
jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
|
||||
jmr3927_dipsw1(), jmr3927_dipsw2(),
|
||||
jmr3927_dipsw3(), jmr3927_dipsw4());
|
||||
}
|
||||
|
||||
/* This trick makes rtc-ds1742 driver usable as is. */
|
||||
|
|
|
@ -123,15 +123,15 @@ static int __init rbtx4938_ethaddr_init(void)
|
|||
|
||||
/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
|
||||
if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
|
||||
printk(KERN_ERR "seeprom: read error.\n");
|
||||
pr_err("seeprom: read error.\n");
|
||||
return -ENODEV;
|
||||
} else {
|
||||
if (strcmp(dat, "MAC") != 0)
|
||||
printk(KERN_WARNING "seeprom: bad signature.\n");
|
||||
pr_warn("seeprom: bad signature.\n");
|
||||
for (i = 0, sum = 0; i < sizeof(dat); i++)
|
||||
sum += dat[i];
|
||||
if (sum)
|
||||
printk(KERN_WARNING "seeprom: bad checksum.\n");
|
||||
pr_warn("seeprom: bad checksum.\n");
|
||||
}
|
||||
tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
|
||||
#endif /* CONFIG_PCI */
|
||||
|
@ -214,14 +214,14 @@ static void __init rbtx4938_mem_setup(void)
|
|||
rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
|
||||
rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||
if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
|
||||
printk(KERN_ERR "request resource for fpga failed\n");
|
||||
pr_err("request resource for fpga failed\n");
|
||||
|
||||
_machine_restart = rbtx4938_machine_restart;
|
||||
|
||||
writeb(0xff, rbtx4938_led_addr);
|
||||
printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
|
||||
readb(rbtx4938_fpga_rev_addr),
|
||||
readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
|
||||
pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
|
||||
readb(rbtx4938_fpga_rev_addr),
|
||||
readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
|
||||
}
|
||||
|
||||
static void __init rbtx4938_ne_init(void)
|
||||
|
|
Loading…
Reference in a new issue