s390/xor: optimized xor routing using the XC instruction
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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#include <asm-generic/xor.h>
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/*
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* Optimited xor routines
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*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef _ASM_S390_XOR_H
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#define _ASM_S390_XOR_H
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extern struct xor_block_template xor_block_xc;
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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xor_speed(&xor_block_xc); \
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} while (0)
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#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_xc)
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#endif /* _ASM_S390_XOR_H */
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@ -3,7 +3,7 @@
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#
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lib-y += delay.o string.o uaccess.o find.o
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obj-y += mem.o
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obj-y += mem.o xor.o
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lib-$(CONFIG_SMP) += spinlock.o
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lib-$(CONFIG_KPROBES) += probes.o
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lib-$(CONFIG_UPROBES) += probes.o
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134
arch/s390/lib/xor.c
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134
arch/s390/lib/xor.c
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/*
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* Optimized xor_block operation for RAID4/5
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*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/raid/xor.h>
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static void xor_xc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3:\n"
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: : "d" (bytes), "a" (p1), "a" (p2)
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: "0", "1", "cc", "memory");
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}
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static void xor_xc_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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"3:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3)
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: : "0", "1", "cc", "memory");
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}
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static void xor_xc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" xc 0(256,%1),0(%4)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" ex %0,12(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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" xc 0(1,%1),0(%4)\n"
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"3:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4)
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: : "0", "1", "cc", "memory");
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}
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static void xor_xc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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{
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/* Get around a gcc oddity */
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register unsigned long *reg7 asm ("7") = p5;
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" xc 0(256,%1),0(%4)\n"
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" xc 0(256,%1),0(%5)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" la %5,256(%5)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" ex %0,12(1)\n"
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" ex %0,18(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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" xc 0(1,%1),0(%4)\n"
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" xc 0(1,%1),0(%5)\n"
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"3:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4),
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"+a" (reg7)
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: : "0", "1", "cc", "memory");
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}
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struct xor_block_template xor_block_xc = {
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.name = "xc",
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.do_2 = xor_xc_2,
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.do_3 = xor_xc_3,
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.do_4 = xor_xc_4,
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.do_5 = xor_xc_5,
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};
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EXPORT_SYMBOL(xor_block_xc);
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