ASoC: rt5645: multiple JD mode support
There are 3 JD modes in RT5645. This patch configure register values according to platform data. Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -26,6 +26,7 @@ struct rt5645_platform_data {
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/* true if codec's jd function is used */
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bool en_jd_func;
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unsigned int jd_mode;
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};
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#endif
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@ -2239,7 +2239,8 @@ static int rt5645_jack_detect(struct snd_soc_codec *codec)
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snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
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snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
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snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
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if (rt5645->pdata.jd_mode == 0)
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snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
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snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
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snd_soc_dapm_sync(&codec->dapm);
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}
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@ -2543,6 +2544,38 @@ static int rt5645_i2c_probe(struct i2c_client *i2c,
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RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
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}
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if (rt5645->pdata.jd_mode) {
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regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
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RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
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regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
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RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
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regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
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RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
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regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
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RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
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regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
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RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
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switch (rt5645->pdata.jd_mode) {
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case 1:
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regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
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RT5645_JD1_MODE_MASK,
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RT5645_JD1_MODE_0);
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break;
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case 2:
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regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
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RT5645_JD1_MODE_MASK,
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RT5645_JD1_MODE_1);
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break;
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case 3:
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regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
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RT5645_JD1_MODE_MASK,
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RT5645_JD1_MODE_2);
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break;
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default:
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break;
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}
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}
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if (rt5645->i2c->irq) {
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ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
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IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
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@ -594,6 +594,7 @@
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#define RT5645_M_DAC1_HM_SFT 14
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#define RT5645_M_HPVOL_HM (0x1 << 13)
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#define RT5645_M_HPVOL_HM_SFT 13
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#define RT5645_IRQ_PSV_MODE (0x1 << 12)
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/* SPK Left Mixer Control (0x46) */
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#define RT5645_G_RM_L_SM_L_MASK (0x3 << 14)
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@ -1350,6 +1351,10 @@
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#define RT5645_PWR_CLK25M_PU (0x1 << 4)
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#define RT5645_IRQ_CLK_MCLK (0x0 << 3)
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#define RT5645_IRQ_CLK_INT (0x1 << 3)
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#define RT5645_JD1_MODE_MASK (0x3 << 0)
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#define RT5645_JD1_MODE_0 (0x0 << 0)
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#define RT5645_JD1_MODE_1 (0x1 << 0)
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#define RT5645_JD1_MODE_2 (0x2 << 0)
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/* VAD Control 4 (0x9d) */
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#define RT5645_VAD_SEL_MASK (0x3 << 8)
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@ -1638,6 +1643,7 @@
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#define RT5645_OT_P_SFT 10
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#define RT5645_OT_P_NOR (0x0 << 10)
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#define RT5645_OT_P_INV (0x1 << 10)
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#define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
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/* IRQ Control 2 (0xbe) */
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#define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
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@ -2120,6 +2126,7 @@ enum {
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#define RT5645_RXDP2_SEL_SFT (3)
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/* General Control3 (0xfc) */
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#define RT5645_JD_PSV_MODE (0x1 << 12)
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#define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
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#define RT5645_MICINDET_MANU (0x1 << 7)
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