drm/etnaviv: add flushing logic for MMUv2
Flushing works differently on MMUv2, in that it's only necessary to set a single bit in the control register to flush all translation units. A semaphore stall then makes sure that the flush has propagated properly. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -276,8 +276,12 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
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extra_dwords = 1;
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/* flush command */
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if (gpu->mmu->need_flush)
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extra_dwords += 1;
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if (gpu->mmu->need_flush) {
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if (gpu->mmu->version == ETNAVIV_IOMMU_V1)
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extra_dwords += 1;
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else
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extra_dwords += 3;
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}
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/* pipe switch commands */
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if (gpu->switch_context)
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@ -287,12 +291,23 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event,
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if (gpu->mmu->need_flush) {
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/* Add the MMU flush */
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
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VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
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VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
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if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {
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CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,
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VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |
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VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |
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VIVS_GL_FLUSH_MMU_FLUSH_UNK4);
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} else {
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CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,
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VIVS_MMUv2_CONFIGURATION_MODE_MASK |
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VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK |
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VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH);
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CMD_SEM(buffer, SYNC_RECIPIENT_FE,
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SYNC_RECIPIENT_PE);
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CMD_STALL(buffer, SYNC_RECIPIENT_FE,
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SYNC_RECIPIENT_PE);
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}
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gpu->mmu->need_flush = false;
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}
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