[POWERPC] mpc52xx suspend to deep-sleep
Implement deep-sleep on MPC52xx. SDRAM is put into self-refresh with help of SRAM code (alternatives would be code in FLASH, I-cache). Interrupt code must also not be in SDRAM, so put it in I-cache. MPC52xx core is static, so contents will remain intact even with clocks turned off. Signed-off-by: Domen Puncer <domen.puncer@telargo.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Domen Puncer
Paul Mackerras
parent
a348119778
commit
2e1ee1f766
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@ -8,3 +8,5 @@ endif
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obj-$(CONFIG_PPC_EFIKA) += efika.o
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obj-$(CONFIG_PPC_LITE5200) += lite5200.o
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obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
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@ -184,6 +184,16 @@ static void efika_show_cpuinfo(struct seq_file *m)
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of_node_put(root);
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}
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#ifdef CONFIG_PM
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static void efika_suspend_prepare(void __iomem *mbar)
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{
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u8 pin = 4; /* GPIO_WKUP_4 (GPIO_PSC6_0 - IRDA_RX) */
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u8 level = 1; /* wakeup on high level */
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/* IOW. to wake it up, short pins 1 and 3 on IRDA connector */
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mpc52xx_set_wakeup_gpio(pin, level);
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}
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#endif
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static void __init efika_setup_arch(void)
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{
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rtas_initialize();
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@ -199,6 +209,11 @@ static void __init efika_setup_arch(void)
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efika_pcisetup();
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#ifdef CONFIG_PM
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mpc52xx_suspend.board_suspend_prepare = efika_suspend_prepare;
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mpc52xx_pm_init();
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#endif
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if (ppc_md.progress)
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ppc_md.progress("Linux/PPC " UTS_RELEASE " running on Efika ;-)\n", 0x0);
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}
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@ -85,6 +85,28 @@ error:
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iounmap(gpio);
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}
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#ifdef CONFIG_PM
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static u32 descr_a;
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static void lite5200_suspend_prepare(void __iomem *mbar)
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{
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u8 pin = 1; /* GPIO_WKUP_1 (GPIO_PSC2_4) */
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u8 level = 0; /* wakeup on low level */
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mpc52xx_set_wakeup_gpio(pin, level);
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/*
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* power down usb port
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* this needs to be called before of-ohci suspend code
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*/
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descr_a = in_be32(mbar + 0x1048);
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out_be32(mbar + 0x1048, (descr_a & ~0x200) | 0x100);
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}
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static void lite5200_resume_finish(void __iomem *mbar)
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{
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out_be32(mbar + 0x1048, descr_a);
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}
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#endif
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static void __init lite5200_setup_arch(void)
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{
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struct device_node *np;
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@ -107,6 +129,12 @@ static void __init lite5200_setup_arch(void)
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mpc52xx_setup_cpu(); /* Generic */
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lite5200_setup_cpu(); /* Platorm specific */
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#ifdef CONFIG_PM
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mpc52xx_suspend.board_suspend_prepare = lite5200_suspend_prepare;
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mpc52xx_suspend.board_resume_finish = lite5200_resume_finish;
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mpc52xx_pm_init();
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#endif
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#ifdef CONFIG_PCI
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np = of_find_node_by_type(NULL, "pci");
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if (np) {
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191
arch/powerpc/platforms/52xx/mpc52xx_pm.c
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191
arch/powerpc/platforms/52xx/mpc52xx_pm.c
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@ -0,0 +1,191 @@
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/io.h>
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#include <asm/time.h>
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#include <asm/cacheflush.h>
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#include <asm/mpc52xx.h>
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#include "mpc52xx_pic.h"
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/* these are defined in mpc52xx_sleep.S, and only used here */
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extern void mpc52xx_deep_sleep(void *sram, void *sdram_regs,
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struct mpc52xx_cdm *, struct mpc52xx_intr *);
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extern void mpc52xx_ds_sram(void);
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extern const long mpc52xx_ds_sram_size;
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extern void mpc52xx_ds_cached(void);
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extern const long mpc52xx_ds_cached_size;
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static void __iomem *mbar;
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static void __iomem *sdram;
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static struct mpc52xx_cdm __iomem *cdm;
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static struct mpc52xx_intr __iomem *intr;
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static struct mpc52xx_gpio_wkup __iomem *gpiow;
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static void *sram;
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static int sram_size;
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struct mpc52xx_suspend mpc52xx_suspend;
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static int mpc52xx_pm_valid(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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return 1;
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default:
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return 0;
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}
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}
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int mpc52xx_set_wakeup_gpio(u8 pin, u8 level)
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{
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u16 tmp;
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/* enable gpio */
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out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin));
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/* set as input */
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out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin));
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/* enable deep sleep interrupt */
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out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin));
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/* low/high level creates wakeup interrupt */
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tmp = in_be16(&gpiow->wkup_itype);
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tmp &= ~(0x3 << (pin * 2));
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tmp |= (!level + 1) << (pin * 2);
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out_be16(&gpiow->wkup_itype, tmp);
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/* master enable */
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out_8(&gpiow->wkup_maste, 1);
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return 0;
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}
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int mpc52xx_pm_prepare(suspend_state_t state)
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{
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if (state != PM_SUSPEND_STANDBY)
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return -EINVAL;
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/* map the whole register space */
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mbar = mpc52xx_find_and_map("mpc5200");
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if (!mbar) {
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printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
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return -ENOSYS;
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}
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/* these offsets are from mpc5200 users manual */
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sdram = mbar + 0x100;
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cdm = mbar + 0x200;
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intr = mbar + 0x500;
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gpiow = mbar + 0xc00;
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sram = mbar + 0x8000; /* Those will be handled by the */
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sram_size = 0x4000; /* bestcomm driver soon */
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/* call board suspend code, if applicable */
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if (mpc52xx_suspend.board_suspend_prepare)
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mpc52xx_suspend.board_suspend_prepare(mbar);
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else {
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printk(KERN_ALERT "%s: %i don't know how to wake up the board\n",
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__func__, __LINE__);
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goto out_unmap;
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}
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return 0;
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out_unmap:
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iounmap(mbar);
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return -ENOSYS;
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}
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char saved_sram[0x4000];
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int mpc52xx_pm_enter(suspend_state_t state)
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{
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u32 clk_enables;
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u32 msr, hid0;
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u32 intr_main_mask;
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void __iomem * irq_0x500 = (void *)CONFIG_KERNEL_START + 0x500;
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unsigned long irq_0x500_stop = (unsigned long)irq_0x500 + mpc52xx_ds_cached_size;
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char saved_0x500[mpc52xx_ds_cached_size];
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/* disable all interrupts in PIC */
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intr_main_mask = in_be32(&intr->main_mask);
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out_be32(&intr->main_mask, intr_main_mask | 0x1ffff);
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/* don't let DEC expire any time soon */
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mtspr(SPRN_DEC, 0x7fffffff);
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/* save SRAM */
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memcpy(saved_sram, sram, sram_size);
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/* copy low level suspend code to sram */
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memcpy(sram, mpc52xx_ds_sram, mpc52xx_ds_sram_size);
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out_8(&cdm->ccs_sleep_enable, 1);
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out_8(&cdm->osc_sleep_enable, 1);
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out_8(&cdm->ccs_qreq_test, 1);
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/* disable all but SDRAM and bestcomm (SRAM) clocks */
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clk_enables = in_be32(&cdm->clk_enables);
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out_be32(&cdm->clk_enables, clk_enables & 0x00088000);
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/* disable power management */
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msr = mfmsr();
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mtmsr(msr & ~MSR_POW);
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/* enable sleep mode, disable others */
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hid0 = mfspr(SPRN_HID0);
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mtspr(SPRN_HID0, (hid0 & ~(HID0_DOZE | HID0_NAP | HID0_DPM)) | HID0_SLEEP);
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/* save original, copy our irq handler, flush from dcache and invalidate icache */
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memcpy(saved_0x500, irq_0x500, mpc52xx_ds_cached_size);
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memcpy(irq_0x500, mpc52xx_ds_cached, mpc52xx_ds_cached_size);
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flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
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/* call low-level sleep code */
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mpc52xx_deep_sleep(sram, sdram, cdm, intr);
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/* restore original irq handler */
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memcpy(irq_0x500, saved_0x500, mpc52xx_ds_cached_size);
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flush_icache_range((unsigned long)irq_0x500, irq_0x500_stop);
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/* restore old power mode */
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mtmsr(msr & ~MSR_POW);
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mtspr(SPRN_HID0, hid0);
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mtmsr(msr);
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out_be32(&cdm->clk_enables, clk_enables);
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out_8(&cdm->ccs_sleep_enable, 0);
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out_8(&cdm->osc_sleep_enable, 0);
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/* restore SRAM */
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memcpy(sram, saved_sram, sram_size);
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/* restart jiffies */
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wakeup_decrementer();
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/* reenable interrupts in PIC */
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out_be32(&intr->main_mask, intr_main_mask);
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return 0;
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}
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int mpc52xx_pm_finish(suspend_state_t state)
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{
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/* call board resume code */
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if (mpc52xx_suspend.board_resume_finish)
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mpc52xx_suspend.board_resume_finish(mbar);
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iounmap(mbar);
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return 0;
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}
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static struct pm_ops mpc52xx_pm_ops = {
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.valid = mpc52xx_pm_valid,
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.prepare = mpc52xx_pm_prepare,
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.enter = mpc52xx_pm_enter,
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.finish = mpc52xx_pm_finish,
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};
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int __init mpc52xx_pm_init(void)
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{
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pm_set_ops(&mpc52xx_pm_ops);
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return 0;
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}
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154
arch/powerpc/platforms/52xx/mpc52xx_sleep.S
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154
arch/powerpc/platforms/52xx/mpc52xx_sleep.S
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@ -0,0 +1,154 @@
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#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/processor.h>
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.text
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_GLOBAL(mpc52xx_deep_sleep)
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mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
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/* enable interrupts */
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mfmsr r7
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ori r7, r7, 0x8000 /* EE */
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mtmsr r7
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sync; isync;
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li r10, 0 /* flag that irq handler sets */
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/* enable tmr7 (or any other) interrupt */
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lwz r8, 0x14(r6) /* intr->main_mask */
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ori r8, r8, 0x1
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xori r8, r8, 0x1
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stw r8, 0x14(r6)
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sync
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/* emulate tmr7 interrupt */
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li r8, 0x1
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stw r8, 0x40(r6) /* intr->main_emulate */
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sync
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/* wait for it to happen */
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1:
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cmpi cr0, r10, 1
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bne cr0, 1b
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/* lock icache */
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mfspr r10, SPRN_HID0
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ori r10, r10, 0x2000
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sync; isync;
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mtspr SPRN_HID0, r10
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sync; isync;
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mflr r9 /* save LR */
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/* jump to sram */
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mtlr r3
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blrl
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mtlr r9 /* restore LR */
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/* unlock icache */
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mfspr r10, SPRN_HID0
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ori r10, r10, 0x2000
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xori r10, r10, 0x2000
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sync; isync;
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mtspr SPRN_HID0, r10
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sync; isync;
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/* return to C code */
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blr
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_GLOBAL(mpc52xx_ds_sram)
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mpc52xx_ds_sram:
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/* put SDRAM into self-refresh */
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lwz r8, 0x4(r4) /* sdram->ctrl */
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oris r8, r8, 0x8000 /* mode_en */
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stw r8, 0x4(r4)
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sync
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ori r8, r8, 0x0002 /* soft_pre */
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stw r8, 0x4(r4)
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sync
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xori r8, r8, 0x0002
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xoris r8, r8, 0x8000 /* !mode_en */
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stw r8, 0x4(r4)
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sync
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oris r8, r8, 0x5000
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xoris r8, r8, 0x4000 /* ref_en !cke */
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stw r8, 0x4(r4)
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sync
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/* disable SDRAM clock */
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lwz r8, 0x14(r5) /* cdm->clkenable */
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ori r8, r8, 0x0008
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xori r8, r8, 0x0008
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stw r8, 0x14(r5)
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sync
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/* put mpc5200 to sleep */
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mfmsr r10
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oris r10, r10, 0x0004 /* POW = 1 */
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sync; isync;
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mtmsr r10
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sync; isync;
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/* enable clock */
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lwz r8, 0x14(r5)
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ori r8, r8, 0x0008
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stw r8, 0x14(r5)
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sync
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/* get ram out of self-refresh */
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lwz r8, 0x4(r4)
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oris r8, r8, 0x5000 /* cke ref_en */
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stw r8, 0x4(r4)
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sync
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blr
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_GLOBAL(mpc52xx_ds_sram_size)
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mpc52xx_ds_sram_size:
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.long $-mpc52xx_ds_sram
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/* ### interrupt handler for wakeup from deep-sleep ### */
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_GLOBAL(mpc52xx_ds_cached)
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mpc52xx_ds_cached:
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mtspr SPRN_SPRG0, r7
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mtspr SPRN_SPRG1, r8
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/* disable emulated interrupt */
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mfspr r7, 311 /* MBAR */
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addi r7, r7, 0x540 /* intr->main_emul */
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li r8, 0
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stw r8, 0(r7)
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sync
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dcbf 0, r7
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/* acknowledge wakeup, so CCS releases power pown */
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mfspr r7, 311 /* MBAR */
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addi r7, r7, 0x524 /* intr->enc_status */
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lwz r8, 0(r7)
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ori r8, r8, 0x0400
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stw r8, 0(r7)
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sync
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dcbf 0, r7
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/* flag - we handled the interrupt */
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li r10, 1
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mfspr r8, SPRN_SPRG1
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mfspr r7, SPRN_SPRG0
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rfi
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_GLOBAL(mpc52xx_ds_cached_size)
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mpc52xx_ds_cached_size:
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.long $-mpc52xx_ds_cached
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@ -253,5 +253,16 @@ extern int __init mpc52xx_add_bridge(struct device_node *node);
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_PM
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struct mpc52xx_suspend {
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void (*board_suspend_prepare)(void __iomem *mbar);
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void (*board_resume_finish)(void __iomem *mbar);
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};
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extern struct mpc52xx_suspend mpc52xx_suspend;
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extern int __init mpc52xx_pm_init(void);
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extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
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#endif /* CONFIG_PM */
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#endif /* __ASM_POWERPC_MPC52xx_H__ */
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