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MLK-15064-1 ARM: imx: pcie: enable imx8 pcie 

- use one standalone hsio node to share the region to
pciea, pcieb and sata.
- axi master slave and dbi clks and pipe_clk are required
- enable pcieb
  change the pd of the pcieb, otherwise, clk is failed to enable
- add the cpu addr offset
  Bit[31:24]
  pciea 60 - 6f ---> 40 - 4f
  pcieb 70 - 7f ---> 80 - 8f

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
pull/10/head
Richard Zhu 2017-05-26 16:41:46 +08:00 committed by Jason Liu
parent 4e263e9ce3
commit 2e56ff43c7
8 changed files with 209 additions and 3 deletions
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15
Documentation/devicetree/bindings/dma/fsl-imx-dma.txt
View File

@ -46,3 +46,18 @@ Example:
dma-names = "rx-tx";
...
};
* DMA capability limitation
Specify the DMA capability limitations.
For example, some SoCs only support up to 32bit DMA capability, although
they are 64bit SoCs.
- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA
capability.
Example:
dma_cap: dma_cap {
compatible = "dma-capability";
only-dma-mask32 = <1>;
};

5
Documentation/devicetree/bindings/mfd/syscon.txt
View File

@ -23,3 +23,8 @@ gpr: iomuxc-gpr@020e0000 {
compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e0000 0x38>;
};
hsio: hsio@5f080000 {
compatible = "fsl,imx8qm-hsio", "syscon";
reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
};

18
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
View File

@ -9,6 +9,7 @@ Required properties:
- "fsl,imx6sx-pcie",
- "fsl,imx6qp-pcie"
- "fsl,imx7d-pcie"
- "fsl,imx8qm-pcie"
- reg: base address and length of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
@ -51,6 +52,23 @@ Additional required properties for imx7d-pcie:
- "pciephy"
- "apps"
Additional required properties for imx8 pcie:
- hsio : should be <&hsio>.
The phandle points to the hsio region containing the hsio
such as the pcie and sata control registers.
- hsio-cfg: hsio configration mode when the pcie node is supported.
mode 1: pciea 2 lanes and one sata ahci port.
mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port.
mode 3: pciea 2 lanes, pcieb 1 lane.
- ctrl-id: used to distinguish pciea or pcieb.
0: pciea, 1: pcieb.
- cpu-base-addr: the base cpu address mapped from hsio address.
Example:
hsio-cfg = <PCIEAX1PCIEBX1SATA>;
hsio = <&hsio>;
ctrl-id = <0>; /* pciea */
cpu-base-addr = <0x40000000>;
Example:
pcie@0x01000000 {

16
arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
View File

@ -313,6 +313,14 @@
SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
>;
};
pinctrl_pciea: pcieagrp{
fsl,pins = <
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021
SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x00000021
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021
>;
};
};
};
@ -538,3 +546,11 @@
&dpu2 {
status = "okay";
};
&pciea{
ext_osc = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pciea>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
};

51
arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
View File

@ -18,6 +18,7 @@
#include "fsl-imx8-ca72.dtsi"
#include <dt-bindings/clock/imx8qm-clock.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <dt-bindings/soc/imx8_hsio.h>
#include <dt-bindings/soc/imx8_pd.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#include <dt-bindings/gpio/gpio.h>
@ -1867,6 +1868,56 @@
ports = <&dpu1_disp0>, <&dpu1_disp1>,
<&dpu2_disp0>, <&dpu2_disp1>;
};
dma_cap: dma_cap {
compatible = "dma-capability";
only-dma-mask32 = <1>;
};
hsio: hsio@5f080000 {
compatible = "fsl,imx8qm-hsio", "syscon";
reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
};
pciea: pcie@0x5f000000 {
compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */
<0x0 0x6ff00000 0x0 0x10000>; /* PCI cfg space */
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
/*
* Set these clocks in default, then clocks should be
* refined for exact hw design of imx8 pcie.
*/
clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
<&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
<&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
<&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 73 4>,
<0 0 0 2 &gic 0 74 4>,
<0 0 0 3 &gic 0 75 4>,
<0 0 0 4 &gic 0 76 4>;
power-domains = <&pd_pcie0>;
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX1PCIEBX1SATA>;
hsio = <&hsio>;
ctrl-id = <0>; /* pciea */
cpu-base-addr = <0x40000000>;
status = "disabled";
};
};
&A53_0 {

16
arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2.dts
View File

@ -281,6 +281,14 @@
SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021
>;
};
pinctrl_pcieb: pcieagrp{
fsl,pins = <
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x06000021
>;
};
};
};
@ -419,3 +427,11 @@
&dpu1 {
status = "okay";
};
&pcieb{
ext_osc = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>;
reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>;
status = "okay";
};

60
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi
View File

@ -16,6 +16,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fsl-imx8-ca35.dtsi"
#include <dt-bindings/soc/imx_rsrc.h>
#include <dt-bindings/soc/imx8_hsio.h>
#include <dt-bindings/soc/imx8_pd.h>
#include <dt-bindings/clock/imx8qxp-clock.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
@ -584,9 +585,8 @@
#address-cells = <1>;
#size-cells = <0>;
pd_pcie: hsio-pcie-pd {
name = "hsio-pcie-pd";
reg = <SC_R_PCIE_A>;
pd_pcie: PD_HSIO_PCIE_B {
reg = <SC_R_PCIE_B>;
#power-domain-cells = <0>;
power-domains =<&pd_hsio>;
};
@ -1399,6 +1399,60 @@
compatible = "fsl,imx-display-subsystem";
ports = <&dpu_disp0>, <&dpu_disp1>;
};
dma_cap: dma_cap {
compatible = "dma-capability";
only-dma-mask32 = <1>;
};
hsio: hsio@5f080000 {
compatible = "fsl,imx8qm-hsio", "syscon";
reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */
};
pcieb: pcie@0x5f010000 {
/*
* pcieb phyx1 lane1 in default, adjust it refer to the
* exact hw design.
*/
compatible = "fsl,imx8qm-pcie","snps,dw-pcie";
reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/
<0x0 0x7ff00000 0x0 0x10000>; /* PCI cfg space */
reg-names = "dbi", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
/*
* Set these clocks in default, then clocks should be
* refined for exact hw design of imx8 pcie.
*/
clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>,
<&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>,
<&clk IMX8QXP_HSIO_PHY_X1_PCLK>,
<&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &gic 0 105 4>,
<0 0 0 2 &gic 0 106 4>,
<0 0 0 3 &gic 0 107 4>,
<0 0 0 4 &gic 0 108 4>;
power-domains = <&pd_pcie>;
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX2PCIEBX1>;
hsio = <&hsio>;
ctrl-id = <1>; /* pcieb */
cpu-base-addr = <0x80000000>;
status = "disabled";
};
};
&A35_0 {

31
include/dt-bindings/soc/imx8_hsio.h 100644
View File

@ -0,0 +1,31 @@
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_IMX8_HSIO_H
#define __DT_BINDINGS_IMX8_HSIO_H
/*
* imx8qm hsio has pciea, pcieb and sata modules, and hsio
* can be configured to the following different work modes.
* 1 - pciea 2 lanes and one sata ahci port.
* 2 - pciea 1 lane, pcieb 1 lane and one sata ahci port.
* 3 - pciea 2 lanes, pcieb 1 lane.
* Choose one mode, refer to the exact hardware board design.
*/
#define PCIEAX2SATA 1
#define PCIEAX1PCIEBX1SATA 2
#define PCIEAX2PCIEBX1 3
#endif /* __DT_BINDINGS_IMX8_HSIO_H */