i40e: use functions to enable and disable icr 0
Introduce i40e_irq_dynamic_disable_icr0 and use it and its previously- extant counterpart when appropriate. Change-Id: Ieb4037874fba2e96fc2354b34a97a3cb8f6490f3 Signed-off-by: Mitch Williams <mitch.a.williams@intel.com> Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com> Tested-by: Sibai Li <sibai.li@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -565,6 +565,7 @@ static inline void i40e_dbg_init(void) {}
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static inline void i40e_dbg_exit(void) {}
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#endif /* CONFIG_DEBUG_FS*/
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void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector);
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void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
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void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
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int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
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void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
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@ -2542,6 +2542,19 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
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i40e_flush(hw);
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}
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/**
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* i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
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* @pf: board private structure
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**/
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void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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wr32(hw, I40E_PFINT_DYN_CTL0,
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I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
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i40e_flush(hw);
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}
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/**
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* i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
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* @pf: board private structure
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@ -719,15 +719,14 @@ static bool i40e_vfs_are_assigned(struct i40e_pf *pf)
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**/
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void i40e_free_vfs(struct i40e_pf *pf)
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{
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struct i40e_hw *hw = &pf->hw;
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int i, tmp;
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if (!pf->vf)
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return;
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/* Disable interrupt 0 so we don't try to handle the VFLR. */
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wr32(hw, I40E_PFINT_DYN_CTL0, 0);
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i40e_flush(hw);
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i40e_irq_dynamic_disable_icr0(pf);
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mdelay(10); /* let any messages in transit get finished up */
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/* free up vf resources */
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tmp = pf->num_alloc_vfs;
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@ -749,11 +748,7 @@ void i40e_free_vfs(struct i40e_pf *pf)
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"unable to disable SR-IOV because VFs are assigned.\n");
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/* Re-enable interrupt 0. */
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wr32(hw, I40E_PFINT_DYN_CTL0,
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I40E_PFINT_DYN_CTL0_INTENA_MASK |
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I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
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(I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT));
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i40e_flush(hw);
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i40e_irq_dynamic_enable_icr0(pf);
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}
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#ifdef CONFIG_PCI_IOV
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@ -766,13 +761,12 @@ void i40e_free_vfs(struct i40e_pf *pf)
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**/
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static int i40e_alloc_vfs(struct i40e_pf *pf, u16 num_alloc_vfs)
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{
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struct i40e_hw *hw = &pf->hw;
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struct i40e_vf *vfs;
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int i, ret = 0;
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/* Disable interrupt 0 so we don't try to handle the VFLR. */
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wr32(hw, I40E_PFINT_DYN_CTL0, 0);
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i40e_flush(hw);
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i40e_irq_dynamic_disable_icr0(pf);
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ret = pci_enable_sriov(pf->pdev, num_alloc_vfs);
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if (ret) {
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dev_err(&pf->pdev->dev,
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@ -810,10 +804,7 @@ err_alloc:
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i40e_free_vfs(pf);
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err_iov:
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/* Re-enable interrupt 0. */
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wr32(hw, I40E_PFINT_DYN_CTL0,
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I40E_PFINT_DYN_CTL0_INTENA_MASK |
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I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
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(I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT));
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i40e_irq_dynamic_enable_icr0(pf);
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return ret;
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}
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