[SCSI] hpsa: Allow multiple command completions per interrupt.
This is done by adding support for the so-called "performant mode" (that's really what they called it). Smart Array controllers have a mode which enables multiple command completions to be delivered with a single interrupt, "performant" mode. We want to use that mode, as some newer controllers will be requiring this mode. Signed-off-by: Don Brace <brace@beardog.cce.hp.com> Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: Mike Miller <mikem@beardog.cce.hp.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
This commit is contained in:
parent
900c54404a
commit
303932fd4f
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@ -150,6 +150,11 @@ static int check_for_unit_attention(struct ctlr_info *h,
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struct CommandList *c);
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static void check_ioctl_unit_attention(struct ctlr_info *h,
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struct CommandList *c);
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/* performant mode helper functions */
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static void calc_bucket_map(int *bucket, int num_buckets,
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int nsgs, int *bucket_map);
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static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
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static inline u32 next_command(struct ctlr_info *h);
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static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
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static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
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@ -173,10 +178,8 @@ static struct scsi_host_template hpsa_driver_template = {
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.name = "hpsa",
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.proc_name = "hpsa",
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.queuecommand = hpsa_scsi_queue_command,
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.can_queue = 512,
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.this_id = -1,
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.sg_tablesize = MAXSGENTRIES,
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.cmd_per_lun = 512,
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.use_clustering = ENABLE_CLUSTERING,
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.eh_device_reset_handler = hpsa_eh_device_reset_handler,
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.ioctl = hpsa_ioctl,
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@ -394,10 +397,44 @@ static inline void addQ(struct hlist_head *list, struct CommandList *c)
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hlist_add_head(&c->list, list);
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}
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static inline u32 next_command(struct ctlr_info *h)
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{
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u32 a;
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if (unlikely(h->transMethod != CFGTBL_Trans_Performant))
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return h->access.command_completed(h);
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if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
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a = *(h->reply_pool_head); /* Next cmd in ring buffer */
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(h->reply_pool_head)++;
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h->commands_outstanding--;
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} else {
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a = FIFO_EMPTY;
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}
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/* Check for wraparound */
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if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
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h->reply_pool_head = h->reply_pool;
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h->reply_pool_wraparound ^= 1;
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}
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return a;
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}
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/* set_performant_mode: Modify the tag for cciss performant
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* set bit 0 for pull model, bits 3-1 for block fetch
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* register number
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*/
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static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
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{
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if (likely(h->transMethod == CFGTBL_Trans_Performant))
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c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
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}
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static void enqueue_cmd_and_start_io(struct ctlr_info *h,
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struct CommandList *c)
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{
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unsigned long flags;
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set_performant_mode(h, c);
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spin_lock_irqsave(&h->lock, flags);
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addQ(&h->reqQ, c);
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h->Qdepth++;
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@ -1116,9 +1153,11 @@ static int hpsa_scsi_detect(struct ctlr_info *h)
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sh->max_cmd_len = MAX_COMMAND_SIZE;
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sh->max_lun = HPSA_MAX_LUN;
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sh->max_id = HPSA_MAX_LUN;
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sh->can_queue = h->nr_cmds;
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sh->cmd_per_lun = h->nr_cmds;
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h->scsi_host = sh;
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sh->hostdata[0] = (unsigned long) h;
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sh->irq = h->intr[SIMPLE_MODE_INT];
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sh->irq = h->intr[PERF_MODE_INT];
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sh->unique_id = sh->irq;
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error = scsi_add_host(sh, &h->pdev->dev);
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if (error)
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@ -1843,7 +1882,8 @@ static int hpsa_scsi_queue_command(struct scsi_cmnd *cmd,
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c->scsi_cmd = cmd;
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c->Header.ReplyQueue = 0; /* unused in simple mode */
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memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
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c->Header.Tag.lower = c->busaddr; /* Use k. address of cmd as tag */
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c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
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c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
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/* Fill in the request block... */
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@ -2700,8 +2740,9 @@ static inline bool interrupt_pending(struct ctlr_info *h)
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static inline long interrupt_not_for_us(struct ctlr_info *h)
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{
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return ((h->access.intr_pending(h) == 0) ||
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(h->interrupts_enabled == 0));
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return !(h->msi_vector || h->msix_vector) &&
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((h->access.intr_pending(h) == 0) ||
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(h->interrupts_enabled == 0));
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}
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static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
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@ -2725,13 +2766,13 @@ static inline void finish_cmd(struct CommandList *c, u32 raw_tag)
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static inline u32 hpsa_tag_contains_index(u32 tag)
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{
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#define DIRECT_LOOKUP_BIT 0x04
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#define DIRECT_LOOKUP_BIT 0x10
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return tag & DIRECT_LOOKUP_BIT;
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}
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static inline u32 hpsa_tag_to_index(u32 tag)
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{
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#define DIRECT_LOOKUP_SHIFT 3
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#define DIRECT_LOOKUP_SHIFT 5
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return tag >> DIRECT_LOOKUP_SHIFT;
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}
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@ -2741,42 +2782,61 @@ static inline u32 hpsa_tag_discard_error_bits(u32 tag)
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return tag & ~HPSA_ERROR_BITS;
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}
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/* process completion of an indexed ("direct lookup") command */
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static inline u32 process_indexed_cmd(struct ctlr_info *h,
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u32 raw_tag)
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{
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u32 tag_index;
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struct CommandList *c;
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tag_index = hpsa_tag_to_index(raw_tag);
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if (bad_tag(h, tag_index, raw_tag))
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return next_command(h);
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c = h->cmd_pool + tag_index;
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finish_cmd(c, raw_tag);
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return next_command(h);
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}
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/* process completion of a non-indexed command */
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static inline u32 process_nonindexed_cmd(struct ctlr_info *h,
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u32 raw_tag)
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{
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u32 tag;
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struct CommandList *c = NULL;
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struct hlist_node *tmp;
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tag = hpsa_tag_discard_error_bits(raw_tag);
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hlist_for_each_entry(c, tmp, &h->cmpQ, list) {
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if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
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finish_cmd(c, raw_tag);
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return next_command(h);
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}
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}
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bad_tag(h, h->nr_cmds + 1, raw_tag);
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return next_command(h);
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}
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static irqreturn_t do_hpsa_intr(int irq, void *dev_id)
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{
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struct ctlr_info *h = dev_id;
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struct CommandList *c;
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unsigned long flags;
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u32 raw_tag, tag, tag_index;
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struct hlist_node *tmp;
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u32 raw_tag;
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if (interrupt_not_for_us(h))
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return IRQ_NONE;
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spin_lock_irqsave(&h->lock, flags);
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while (interrupt_pending(h)) {
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while ((raw_tag = get_next_completion(h)) != FIFO_EMPTY) {
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if (likely(hpsa_tag_contains_index(raw_tag))) {
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tag_index = hpsa_tag_to_index(raw_tag);
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if (bad_tag(h, tag_index, raw_tag))
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return IRQ_HANDLED;
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c = h->cmd_pool + tag_index;
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finish_cmd(c, raw_tag);
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continue;
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}
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tag = hpsa_tag_discard_error_bits(raw_tag);
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c = NULL;
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hlist_for_each_entry(c, tmp, &h->cmpQ, list) {
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if (c->busaddr == tag) {
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finish_cmd(c, raw_tag);
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break;
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}
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}
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}
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raw_tag = get_next_completion(h);
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while (raw_tag != FIFO_EMPTY) {
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if (hpsa_tag_contains_index(raw_tag))
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raw_tag = process_indexed_cmd(h, raw_tag);
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else
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raw_tag = process_nonindexed_cmd(h, raw_tag);
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}
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spin_unlock_irqrestore(&h->lock, flags);
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return IRQ_HANDLED;
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}
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/* Send a message CDB to the firmware. */
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/* Send a message CDB to the firmwart. */
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static __devinit int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
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unsigned char type)
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{
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@ -3108,7 +3168,7 @@ static void __devinit hpsa_interrupt_mode(struct ctlr_info *h,
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default_int_mode:
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#endif /* CONFIG_PCI_MSI */
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/* if we get here we're going to use the default interrupt mode */
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h->intr[SIMPLE_MODE_INT] = pdev->irq;
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h->intr[PERF_MODE_INT] = pdev->irq;
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}
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static int hpsa_pci_init(struct ctlr_info *h, struct pci_dev *pdev)
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@ -3118,6 +3178,7 @@ static int hpsa_pci_init(struct ctlr_info *h, struct pci_dev *pdev)
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u64 cfg_offset;
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u32 cfg_base_addr;
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u64 cfg_base_addr_index;
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u32 trans_offset;
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int i, prod_index, err;
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subsystem_vendor_id = pdev->subsystem_vendor;
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@ -3211,11 +3272,14 @@ static int hpsa_pci_init(struct ctlr_info *h, struct pci_dev *pdev)
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h->cfgtable = remap_pci_mem(pci_resource_start(pdev,
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cfg_base_addr_index) + cfg_offset,
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sizeof(h->cfgtable));
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/* Find performant mode table. */
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trans_offset = readl(&(h->cfgtable->TransMethodOffset));
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h->transtable = remap_pci_mem(pci_resource_start(pdev,
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cfg_base_addr_index)+cfg_offset+trans_offset,
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sizeof(*h->transtable));
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h->board_id = board_id;
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/* Query controller for max supported commands: */
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h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
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h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
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h->product_name = products[prod_index].product_name;
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h->access = *(products[prod_index].access);
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/* Allow room for some ioctls */
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@ -3314,7 +3378,12 @@ static int __devinit hpsa_init_one(struct pci_dev *pdev,
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}
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}
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BUILD_BUG_ON(sizeof(struct CommandList) % 8);
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/* Command structures must be aligned on a 32-byte boundary because
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* the 5 lower bits of the address are used by the hardware. and by
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* the driver. See comments in hpsa.h for more info.
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*/
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#define COMMANDLIST_ALIGNMENT 32
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BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
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h = kzalloc(sizeof(*h), GFP_KERNEL);
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if (!h)
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return -ENOMEM;
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@ -3349,17 +3418,17 @@ static int __devinit hpsa_init_one(struct pci_dev *pdev,
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/* make sure the board interrupts are off */
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h->access.set_intr_mask(h, HPSA_INTR_OFF);
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rc = request_irq(h->intr[SIMPLE_MODE_INT], do_hpsa_intr,
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IRQF_DISABLED | IRQF_SHARED, h->devname, h);
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rc = request_irq(h->intr[PERF_MODE_INT], do_hpsa_intr,
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IRQF_DISABLED, h->devname, h);
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if (rc) {
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dev_err(&pdev->dev, "unable to get irq %d for %s\n",
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h->intr[SIMPLE_MODE_INT], h->devname);
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h->intr[PERF_MODE_INT], h->devname);
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goto clean2;
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}
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dev_info(&pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
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h->devname, pdev->device, pci_name(pdev),
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h->intr[SIMPLE_MODE_INT], dac ? "" : " not");
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dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
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h->devname, pdev->device,
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h->intr[PERF_MODE_INT], dac ? "" : " not");
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h->cmd_pool_bits =
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kmalloc(((h->nr_cmds + BITS_PER_LONG -
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@ -3389,6 +3458,7 @@ static int __devinit hpsa_init_one(struct pci_dev *pdev,
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/* Turn the interrupts on so we can service requests */
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h->access.set_intr_mask(h, HPSA_INTR_ON);
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hpsa_put_ctlr_into_performant_mode(h);
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hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
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h->busy_initializing = 0;
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return 1;
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@ -3404,7 +3474,7 @@ clean4:
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h->nr_cmds * sizeof(struct ErrorInfo),
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h->errinfo_pool,
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h->errinfo_pool_dhandle);
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free_irq(h->intr[SIMPLE_MODE_INT], h);
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free_irq(h->intr[PERF_MODE_INT], h);
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clean2:
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clean1:
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h->busy_initializing = 0;
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@ -3448,7 +3518,7 @@ static void hpsa_shutdown(struct pci_dev *pdev)
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*/
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hpsa_flush_cache(h);
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h->access.set_intr_mask(h, HPSA_INTR_OFF);
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free_irq(h->intr[2], h);
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free_irq(h->intr[PERF_MODE_INT], h);
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#ifdef CONFIG_PCI_MSI
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if (h->msix_vector)
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pci_disable_msix(h->pdev);
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@ -3477,7 +3547,10 @@ static void __devexit hpsa_remove_one(struct pci_dev *pdev)
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pci_free_consistent(h->pdev,
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h->nr_cmds * sizeof(struct ErrorInfo),
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h->errinfo_pool, h->errinfo_pool_dhandle);
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pci_free_consistent(h->pdev, h->reply_pool_size,
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h->reply_pool, h->reply_pool_dhandle);
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kfree(h->cmd_pool_bits);
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kfree(h->blockFetchTable);
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/*
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* Deliberately omit pci_disable_device(): it does something nasty to
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* Smart Array controllers that pci_enable_device does not undo
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@ -3509,6 +3582,129 @@ static struct pci_driver hpsa_pci_driver = {
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.resume = hpsa_resume,
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};
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/* Fill in bucket_map[], given nsgs (the max number of
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* scatter gather elements supported) and bucket[],
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* which is an array of 8 integers. The bucket[] array
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* contains 8 different DMA transfer sizes (in 16
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* byte increments) which the controller uses to fetch
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* commands. This function fills in bucket_map[], which
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* maps a given number of scatter gather elements to one of
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* the 8 DMA transfer sizes. The point of it is to allow the
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* controller to only do as much DMA as needed to fetch the
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* command, with the DMA transfer size encoded in the lower
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* bits of the command address.
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*/
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static void calc_bucket_map(int bucket[], int num_buckets,
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int nsgs, int *bucket_map)
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{
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int i, j, b, size;
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/* even a command with 0 SGs requires 4 blocks */
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#define MINIMUM_TRANSFER_BLOCKS 4
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#define NUM_BUCKETS 8
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/* Note, bucket_map must have nsgs+1 entries. */
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for (i = 0; i <= nsgs; i++) {
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/* Compute size of a command with i SG entries */
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size = i + MINIMUM_TRANSFER_BLOCKS;
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b = num_buckets; /* Assume the biggest bucket */
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/* Find the bucket that is just big enough */
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for (j = 0; j < 8; j++) {
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if (bucket[j] >= size) {
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b = j;
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break;
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}
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}
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/* for a command with i SG entries, use bucket b. */
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bucket_map[i] = b;
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}
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}
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static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
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{
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u32 trans_support;
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u64 trans_offset;
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/* 5 = 1 s/g entry or 4k
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* 6 = 2 s/g entry or 8k
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* 8 = 4 s/g entry or 16k
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* 10 = 6 s/g entry or 24k
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*/
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int bft[8] = {5, 6, 8, 10, 12, 20, 28, 35}; /* for scatter/gathers */
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int i = 0;
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int l = 0;
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unsigned long register_value;
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trans_support = readl(&(h->cfgtable->TransportSupport));
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if (!(trans_support & PERFORMANT_MODE))
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return;
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h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
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h->max_sg_entries = 32;
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/* Performant mode ring buffer and supporting data structures */
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h->reply_pool_size = h->max_commands * sizeof(u64);
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h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
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&(h->reply_pool_dhandle));
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/* Need a block fetch table for performant mode */
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h->blockFetchTable = kmalloc(((h->max_sg_entries+1) *
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sizeof(u32)), GFP_KERNEL);
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if ((h->reply_pool == NULL)
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|| (h->blockFetchTable == NULL))
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goto clean_up;
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h->reply_pool_wraparound = 1; /* spec: init to 1 */
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/* Controller spec: zero out this buffer. */
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memset(h->reply_pool, 0, h->reply_pool_size);
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h->reply_pool_head = h->reply_pool;
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trans_offset = readl(&(h->cfgtable->TransMethodOffset));
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bft[7] = h->max_sg_entries + 4;
|
||||
calc_bucket_map(bft, ARRAY_SIZE(bft), 32, h->blockFetchTable);
|
||||
for (i = 0; i < 8; i++)
|
||||
writel(bft[i], &h->transtable->BlockFetch[i]);
|
||||
|
||||
/* size of controller ring buffer */
|
||||
writel(h->max_commands, &h->transtable->RepQSize);
|
||||
writel(1, &h->transtable->RepQCount);
|
||||
writel(0, &h->transtable->RepQCtrAddrLow32);
|
||||
writel(0, &h->transtable->RepQCtrAddrHigh32);
|
||||
writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
|
||||
writel(0, &h->transtable->RepQAddr0High32);
|
||||
writel(CFGTBL_Trans_Performant,
|
||||
&(h->cfgtable->HostWrite.TransportRequest));
|
||||
writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
|
||||
/* under certain very rare conditions, this can take awhile.
|
||||
* (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
|
||||
* as we enter this code.) */
|
||||
for (l = 0; l < MAX_CONFIG_WAIT; l++) {
|
||||
register_value = readl(h->vaddr + SA5_DOORBELL);
|
||||
if (!(register_value & CFGTBL_ChangeReq))
|
||||
break;
|
||||
/* delay and try again */
|
||||
set_current_state(TASK_INTERRUPTIBLE);
|
||||
schedule_timeout(10);
|
||||
}
|
||||
register_value = readl(&(h->cfgtable->TransportActive));
|
||||
if (!(register_value & CFGTBL_Trans_Performant)) {
|
||||
dev_warn(&h->pdev->dev, "unable to get board into"
|
||||
" performant mode\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Change the access methods to the performant access methods */
|
||||
h->access = SA5_performant_access;
|
||||
h->transMethod = CFGTBL_Trans_Performant;
|
||||
|
||||
return;
|
||||
|
||||
clean_up:
|
||||
if (h->reply_pool)
|
||||
pci_free_consistent(h->pdev, h->reply_pool_size,
|
||||
h->reply_pool, h->reply_pool_dhandle);
|
||||
kfree(h->blockFetchTable);
|
||||
}
|
||||
|
||||
/*
|
||||
* This is it. Register the PCI driver information for the cards we control
|
||||
* the OS will call our registered routines when it finds one of our cards.
|
||||
|
|
|
@ -60,14 +60,15 @@ struct ctlr_info {
|
|||
unsigned long paddr;
|
||||
int nr_cmds; /* Number of commands allowed on this controller */
|
||||
struct CfgTable __iomem *cfgtable;
|
||||
int max_sg_entries;
|
||||
int interrupts_enabled;
|
||||
int major;
|
||||
int max_commands;
|
||||
int commands_outstanding;
|
||||
int max_outstanding; /* Debug */
|
||||
int usage_count; /* number of opens all all minor devices */
|
||||
# define DOORBELL_INT 0
|
||||
# define PERF_MODE_INT 1
|
||||
# define PERF_MODE_INT 0
|
||||
# define DOORBELL_INT 1
|
||||
# define SIMPLE_MODE_INT 2
|
||||
# define MEMQ_MODE_INT 3
|
||||
unsigned int intr[4];
|
||||
|
@ -102,6 +103,23 @@ struct ctlr_info {
|
|||
int ndevices; /* number of used elements in .dev[] array. */
|
||||
#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
|
||||
struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
|
||||
/*
|
||||
* Performant mode tables.
|
||||
*/
|
||||
u32 trans_support;
|
||||
u32 trans_offset;
|
||||
struct TransTable_struct *transtable;
|
||||
unsigned long transMethod;
|
||||
|
||||
/*
|
||||
* Performant mode completion buffer
|
||||
*/
|
||||
u64 *reply_pool;
|
||||
dma_addr_t reply_pool_dhandle;
|
||||
u64 *reply_pool_head;
|
||||
size_t reply_pool_size;
|
||||
unsigned char reply_pool_wraparound;
|
||||
u32 *blockFetchTable;
|
||||
};
|
||||
#define HPSA_ABORT_MSG 0
|
||||
#define HPSA_DEVICE_RESET_MSG 1
|
||||
|
@ -165,6 +183,16 @@ struct ctlr_info {
|
|||
|
||||
#define HPSA_ERROR_BIT 0x02
|
||||
|
||||
/* Performant mode flags */
|
||||
#define SA5_PERF_INTR_PENDING 0x04
|
||||
#define SA5_PERF_INTR_OFF 0x05
|
||||
#define SA5_OUTDB_STATUS_PERF_BIT 0x01
|
||||
#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
|
||||
#define SA5_OUTDB_CLEAR 0xA0
|
||||
#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
|
||||
#define SA5_OUTDB_STATUS 0x9C
|
||||
|
||||
|
||||
#define HPSA_INTR_ON 1
|
||||
#define HPSA_INTR_OFF 0
|
||||
/*
|
||||
|
@ -173,7 +201,8 @@ struct ctlr_info {
|
|||
static void SA5_submit_command(struct ctlr_info *h,
|
||||
struct CommandList *c)
|
||||
{
|
||||
dev_dbg(&h->pdev->dev, "Sending %x\n", c->busaddr);
|
||||
dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
|
||||
c->Header.Tag.lower);
|
||||
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
|
||||
h->commands_outstanding++;
|
||||
if (h->commands_outstanding > h->max_outstanding)
|
||||
|
@ -196,6 +225,52 @@ static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
|
|||
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
|
||||
{
|
||||
if (val) { /* turn on interrupts */
|
||||
h->interrupts_enabled = 1;
|
||||
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
|
||||
} else {
|
||||
h->interrupts_enabled = 0;
|
||||
writel(SA5_PERF_INTR_OFF,
|
||||
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned long SA5_performant_completed(struct ctlr_info *h)
|
||||
{
|
||||
unsigned long register_value = FIFO_EMPTY;
|
||||
|
||||
/* flush the controller write of the reply queue by reading
|
||||
* outbound doorbell status register.
|
||||
*/
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
/* msi auto clears the interrupt pending bit. */
|
||||
if (!(h->msi_vector || h->msix_vector)) {
|
||||
writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
|
||||
/* Do a read in order to flush the write to the controller
|
||||
* (as per spec.)
|
||||
*/
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
}
|
||||
|
||||
if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
|
||||
register_value = *(h->reply_pool_head);
|
||||
(h->reply_pool_head)++;
|
||||
h->commands_outstanding--;
|
||||
} else {
|
||||
register_value = FIFO_EMPTY;
|
||||
}
|
||||
/* Check for wraparound */
|
||||
if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
|
||||
h->reply_pool_head = h->reply_pool;
|
||||
h->reply_pool_wraparound ^= 1;
|
||||
}
|
||||
|
||||
return register_value;
|
||||
}
|
||||
|
||||
/*
|
||||
* Returns true if fifo is full.
|
||||
*
|
||||
|
@ -241,6 +316,20 @@ static bool SA5_intr_pending(struct ctlr_info *h)
|
|||
return register_value & SA5_INTR_PENDING;
|
||||
}
|
||||
|
||||
static bool SA5_performant_intr_pending(struct ctlr_info *h)
|
||||
{
|
||||
unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
|
||||
|
||||
if (!register_value)
|
||||
return false;
|
||||
|
||||
if (h->msi_vector || h->msix_vector)
|
||||
return true;
|
||||
|
||||
/* Read outbound doorbell to flush */
|
||||
register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
|
||||
return register_value & SA5_OUTDB_STATUS_PERF_BIT;
|
||||
}
|
||||
|
||||
static struct access_method SA5_access = {
|
||||
SA5_submit_command,
|
||||
|
@ -250,14 +339,19 @@ static struct access_method SA5_access = {
|
|||
SA5_completed,
|
||||
};
|
||||
|
||||
static struct access_method SA5_performant_access = {
|
||||
SA5_submit_command,
|
||||
SA5_performant_intr_mask,
|
||||
SA5_fifo_full,
|
||||
SA5_performant_intr_pending,
|
||||
SA5_performant_completed,
|
||||
};
|
||||
|
||||
struct board_type {
|
||||
u32 board_id;
|
||||
char *product_name;
|
||||
struct access_method *access;
|
||||
};
|
||||
|
||||
|
||||
/* end of old hpsa_scsi.h file */
|
||||
|
||||
#endif /* HPSA_H */
|
||||
|
||||
|
|
|
@ -101,6 +101,7 @@
|
|||
#define CFGTBL_AccCmds 0x00000001l
|
||||
|
||||
#define CFGTBL_Trans_Simple 0x00000002l
|
||||
#define CFGTBL_Trans_Performant 0x00000004l
|
||||
|
||||
#define CFGTBL_BusType_Ultra2 0x00000001l
|
||||
#define CFGTBL_BusType_Ultra3 0x00000002l
|
||||
|
@ -267,12 +268,31 @@ struct ErrorInfo {
|
|||
#define CMD_IOCTL_PEND 0x01
|
||||
#define CMD_SCSI 0x03
|
||||
|
||||
struct ctlr_info; /* defined in hpsa.h */
|
||||
/* The size of this structure needs to be divisible by 8
|
||||
* on all architectures, because the controller uses 2
|
||||
* lower bits of the address, and the driver uses 1 lower
|
||||
* bit (3 bits total.)
|
||||
/* This structure needs to be divisible by 32 for new
|
||||
* indexing method and performant mode.
|
||||
*/
|
||||
#define PAD32 32
|
||||
#define PAD64DIFF 0
|
||||
#define USEEXTRA ((sizeof(void *) - 4)/4)
|
||||
#define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA)
|
||||
|
||||
#define DIRECT_LOOKUP_SHIFT 5
|
||||
#define DIRECT_LOOKUP_BIT 0x10
|
||||
|
||||
#define HPSA_ERROR_BIT 0x02
|
||||
struct ctlr_info; /* defined in hpsa.h */
|
||||
/* The size of this structure needs to be divisible by 32
|
||||
* on all architectures because low 5 bits of the addresses
|
||||
* are used as follows:
|
||||
*
|
||||
* bit 0: to device, used to indicate "performant mode" command
|
||||
* from device, indidcates error status.
|
||||
* bit 1-3: to device, indicates block fetch table entry for
|
||||
* reducing DMA in fetching commands from host memory.
|
||||
* bit 4: used to indicate whether tag is "direct lookup" (index),
|
||||
* or a bus address.
|
||||
*/
|
||||
|
||||
struct CommandList {
|
||||
struct CommandListHeader Header;
|
||||
struct RequestBlock Request;
|
||||
|
@ -291,6 +311,14 @@ struct CommandList {
|
|||
struct completion *waiting;
|
||||
int retry_count;
|
||||
void *scsi_cmd;
|
||||
|
||||
/* on 64 bit architectures, to get this to be 32-byte-aligned
|
||||
* it so happens we need no padding, on 32 bit systems,
|
||||
* we need 8 bytes of padding. This does that.
|
||||
*/
|
||||
#define COMMANDLIST_PAD ((8 - sizeof(long))/4 * 8)
|
||||
u8 pad[COMMANDLIST_PAD];
|
||||
|
||||
};
|
||||
|
||||
/* Configuration Table Structure */
|
||||
|
@ -301,18 +329,38 @@ struct HostWrite {
|
|||
u32 CoalIntCount;
|
||||
};
|
||||
|
||||
#define SIMPLE_MODE 0x02
|
||||
#define PERFORMANT_MODE 0x04
|
||||
#define MEMQ_MODE 0x08
|
||||
|
||||
struct CfgTable {
|
||||
u8 Signature[4];
|
||||
u32 SpecValence;
|
||||
u32 TransportSupport;
|
||||
u32 TransportActive;
|
||||
struct HostWrite HostWrite;
|
||||
u32 CmdsOutMax;
|
||||
u32 BusTypes;
|
||||
u32 Reserved;
|
||||
u8 ServerName[16];
|
||||
u32 HeartBeat;
|
||||
u32 SCSI_Prefetch;
|
||||
u8 Signature[4];
|
||||
u32 SpecValence;
|
||||
u32 TransportSupport;
|
||||
u32 TransportActive;
|
||||
struct HostWrite HostWrite;
|
||||
u32 CmdsOutMax;
|
||||
u32 BusTypes;
|
||||
u32 TransMethodOffset;
|
||||
u8 ServerName[16];
|
||||
u32 HeartBeat;
|
||||
u32 SCSI_Prefetch;
|
||||
u32 MaxScatterGatherElements;
|
||||
u32 MaxLogicalUnits;
|
||||
u32 MaxPhysicalDevices;
|
||||
u32 MaxPhysicalDrivesPerLogicalUnit;
|
||||
u32 MaxPerformantModeCommands;
|
||||
};
|
||||
|
||||
#define NUM_BLOCKFETCH_ENTRIES 8
|
||||
struct TransTable_struct {
|
||||
u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES];
|
||||
u32 RepQSize;
|
||||
u32 RepQCount;
|
||||
u32 RepQCtrAddrLow32;
|
||||
u32 RepQCtrAddrHigh32;
|
||||
u32 RepQAddr0Low32;
|
||||
u32 RepQAddr0High32;
|
||||
};
|
||||
|
||||
struct hpsa_pci_info {
|
||||
|
|
Loading…
Reference in a new issue