From 446bd7dd922edd033d28ef9aa8c594c1c2d05289 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Sep 2016 00:50:30 +0300 Subject: [PATCH 1/7] pinctrl: sh-pfc: r8a7792: Add QSPI pin groups Add QSPI pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 33 ++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 92c670992b3d..0a3e4e03259b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1034,6 +1034,29 @@ static const unsigned int lbsc_ex_cs5_pins[] = { static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; +/* - QSPI ------------------------------------------------------------------- */ +static const unsigned int qspi_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), +}; +static const unsigned int qspi_ctrl_mux[] = { + SPCLK_MARK, SSL_MARK, +}; +static const unsigned int qspi_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), +}; +static const unsigned int qspi_data2_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, +}; +static const unsigned int qspi_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23), + RCAR_GP_PIN(3, 24), +}; +static const unsigned int qspi_data4_mux[] = { + MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -1585,6 +1608,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1708,6 +1734,12 @@ static const char * const lbsc_groups[] = { "lbsc_ex_cs5", }; +static const char * const qspi_groups[] = { + "qspi_ctrl", + "qspi_data2", + "qspi_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -1808,6 +1840,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(sdhi0), From c30716894e96ed1e76bf32ae68c5438350700496 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 5 Sep 2016 23:17:31 +0300 Subject: [PATCH 2/7] pinctrl: sh-pfc: r8a7792: Add MSIOF pin groups Add MSIOF0/1 pin groups to the R8A7792 PFC driver. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7792.c | 82 ++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 0a3e4e03259b..21badb6166b9 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1034,6 +1034,64 @@ static const unsigned int lbsc_ex_cs5_pins[] = { static const unsigned int lbsc_ex_cs5_mux[] = { EX_CS5_N_MARK, }; +/* - MSIOF0 ----------------------------------------------------------------- */ +static const unsigned int msiof0_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 0), +}; +static const unsigned int msiof0_clk_mux[] = { + MSIOF0_SCK_MARK, +}; +static const unsigned int msiof0_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(10, 1), +}; +static const unsigned int msiof0_sync_mux[] = { + MSIOF0_SYNC_MARK, +}; +static const unsigned int msiof0_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(10, 4), +}; +static const unsigned int msiof0_rx_mux[] = { + MSIOF0_RXD_MARK, +}; +static const unsigned int msiof0_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(10, 3), +}; +static const unsigned int msiof0_tx_mux[] = { + MSIOF0_TXD_MARK, +}; +/* - MSIOF1 ----------------------------------------------------------------- */ +static const unsigned int msiof1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 5), +}; +static const unsigned int msiof1_clk_mux[] = { + MSIOF1_SCK_MARK, +}; +static const unsigned int msiof1_sync_pins[] = { + /* SYNC */ + RCAR_GP_PIN(10, 6), +}; +static const unsigned int msiof1_sync_mux[] = { + MSIOF1_SYNC_MARK, +}; +static const unsigned int msiof1_rx_pins[] = { + /* RXD */ + RCAR_GP_PIN(10, 9), +}; +static const unsigned int msiof1_rx_mux[] = { + MSIOF1_RXD_MARK, +}; +static const unsigned int msiof1_tx_pins[] = { + /* TXD */ + RCAR_GP_PIN(10, 8), +}; +static const unsigned int msiof1_tx_mux[] = { + MSIOF1_TXD_MARK, +}; /* - QSPI ------------------------------------------------------------------- */ static const unsigned int qspi_ctrl_pins[] = { /* SPCLK, SSL */ @@ -1608,6 +1666,14 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(lbsc_ex_cs3), SH_PFC_PIN_GROUP(lbsc_ex_cs4), SH_PFC_PIN_GROUP(lbsc_ex_cs5), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), SH_PFC_PIN_GROUP(qspi_ctrl), SH_PFC_PIN_GROUP(qspi_data2), SH_PFC_PIN_GROUP(qspi_data4), @@ -1734,6 +1800,20 @@ static const char * const lbsc_groups[] = { "lbsc_ex_cs5", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_rx", + "msiof0_tx", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_rx", + "msiof1_tx", +}; + static const char * const qspi_groups[] = { "qspi_ctrl", "qspi_data2", @@ -1840,6 +1920,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(intc), SH_PFC_FUNCTION(lbsc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif3), From 40ade582194668aa4336a30f96c9d592c46a1928 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Tue, 6 Sep 2016 17:14:14 +0200 Subject: [PATCH 3/7] pinctrl: sh-pfc: Return pinconf with arguments in packed format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The pinconf-generic code expects configurations with arguments to be returned in a packed format in order to be displayed properly by pinconf_generic_dump_one(). Reading /sys/kernel/debug/pinctrl/e6060000.pfc/pinconf-pins on r8a7795/salvator-x now shows: pin 101 (GP_3_5): output drive strength (9 mA), pin power source (3300 selector) Instead of: pin 101 (GP_3_5): output drive strength (0 mA), pin power source (0 selector) Signed-off-by: Niklas Söderlund Tested-by: Geert Uytterhoeven Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pinctrl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index e208ee04a9f4..c5772584594c 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -596,6 +596,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, struct sh_pfc *pfc = pmx->pfc; enum pin_config_param param = pinconf_to_config_param(*config); unsigned long flags; + unsigned int arg; if (!sh_pfc_pinconf_validate(pfc, _pin, param)) return -ENOTSUPP; @@ -616,7 +617,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (bias != param) return -EINVAL; - *config = 0; + arg = 0; break; } @@ -627,7 +628,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, if (ret < 0) return ret; - *config = ret; + arg = ret; break; } @@ -646,7 +647,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, val = sh_pfc_read_reg(pfc, pocctrl, 32); spin_unlock_irqrestore(&pfc->lock, flags); - *config = (val & BIT(bit)) ? 3300 : 1800; + arg = (val & BIT(bit)) ? 3300 : 1800; break; } @@ -654,6 +655,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, return -ENOTSUPP; } + *config = pinconf_to_config_packed(param, arg); return 0; } From c5901bdcbc6142b686b15d0b4a959aa19a350af1 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 8 Sep 2016 13:57:33 +0200 Subject: [PATCH 4/7] pinctrl: sh-pfc: r8a7796: Add voltage switch operations for SDHI This patch supports the {get,set}_io_voltage operations of SDHI. This operates the POCCTRL0 register on R8A7796 SoC and makes 1.8v/3.3v voltage switch. Based on work by Takeshi Kihara and Wolfram Sang. Cc: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index f8ab74dd0506..dc9b671ccf2e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -23,8 +23,12 @@ PORT_GP_16(0, fn, sfx), \ PORT_GP_29(1, fn, sfx), \ PORT_GP_15(2, fn, sfx), \ - PORT_GP_16(3, fn, sfx), \ - PORT_GP_18(4, fn, sfx), \ + PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(3, 12, fn, sfx), \ + PORT_GP_1(3, 13, fn, sfx), \ + PORT_GP_1(3, 14, fn, sfx), \ + PORT_GP_1(3, 15, fn, sfx), \ + PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ PORT_GP_26(5, fn, sfx), \ PORT_GP_32(6, fn, sfx), \ PORT_GP_4(7, fn, sfx) @@ -2627,8 +2631,28 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + int bit = -EINVAL; + + *pocctrl = 0xe6060380; + + if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) + bit = pin & 0x1f; + + if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17)) + bit = (pin & 0x1f) + 12; + + return bit; +} + +static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { + .pin_to_pocctrl = r8a7796_pin_to_pocctrl, +}; + const struct sh_pfc_soc_info r8a7796_pinmux_info = { .name = "r8a77960_pfc", + .ops = &r8a7796_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, From 9a6caa13f85e8ed7f2079acd8fe01a8d11ab3413 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Sep 2016 09:36:33 +0200 Subject: [PATCH 5/7] pinctrl: sh-pfc: Add PORT_GP_24 helper macro This follows the style of existing PORT_GP_X macros and will be used by a follow-up patch for the r8a7791 SoC. Signed-off-by: Simon Horman Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index c24067edcec4..2345421103db 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -422,9 +422,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info; PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) -#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ PORT_GP_CFG_23(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) +#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) + +#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ + PORT_GP_CFG_24(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) From 0e1396f101da63c1ea3a1868d6e549f3ca20dd5b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Sep 2016 09:36:34 +0200 Subject: [PATCH 6/7] pinctrl: sh-pfc: r8a7791: Implement voltage switching for SDHI All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman Acked-by: Wolfram Sang Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 29 +++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 0c1a60c9a844..7ca37c3019ab 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -13,6 +13,10 @@ #include "sh_pfc.h" +/* + * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in + * which case they support both 3.3V and 1.8V signalling. + */ #define CPU_ALL_PORT(fn, sfx) \ PORT_GP_32(0, fn, sfx), \ PORT_GP_26(1, fn, sfx), \ @@ -20,7 +24,15 @@ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_32(5, fn, sfx), \ - PORT_GP_32(6, fn, sfx), \ + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(6, 24, fn, sfx), \ + PORT_GP_1(6, 25, fn, sfx), \ + PORT_GP_1(6, 26, fn, sfx), \ + PORT_GP_1(6, 27, fn, sfx), \ + PORT_GP_1(6, 28, fn, sfx), \ + PORT_GP_1(6, 29, fn, sfx), \ + PORT_GP_1(6, 30, fn, sfx), \ + PORT_GP_1(6, 31, fn, sfx), \ PORT_GP_26(7, fn, sfx) enum { @@ -6404,9 +6416,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) + return -EINVAL; + + *pocctrl = 0xe606008c; + + return 31 - (pin & 0x1f); +} + +static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { + .pin_to_pocctrl = r8a7791_pin_to_pocctrl, +}; + #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", + .ops = &r8a7791_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, From 77fd4136e58c642482f03d293d5717658a569b4b Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Mon, 12 Sep 2016 09:36:35 +0200 Subject: [PATCH 7/7] pinctrl: sh-pfc: r8a7794: Implement voltage switching for SDHI All the SHDIs can operate with either 3.3V or 1.8V signals, depending on negotiation with the card. Based on work by Wolfram Sang for the r8a7790. Signed-off-by: Simon Horman Acked-by: Wolfram Sang Acked-by: Linus Walleij Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 8bc2cf0c594e..ed734f560c84 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -22,7 +22,9 @@ PORT_GP_32(3, fn, sfx), \ PORT_GP_32(4, fn, sfx), \ PORT_GP_28(5, fn, sfx), \ - PORT_GP_26(6, fn, sfx) + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_1(6, 24, fn, sfx), \ + PORT_GP_1(6, 25, fn, sfx) enum { PINMUX_RESERVED = 0, @@ -5160,8 +5162,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +{ + *pocctrl = 0xe606006c; + + switch (pin & 0x1f) { + case 6: return 23; + case 7: return 16; + case 14: return 15; + case 15: return 8; + case 0 ... 5: + case 8 ... 13: + return 22 - (pin & 0x1f); + case 16 ... 23: + return 47 - (pin & 0x1f); + } + + return -EINVAL; +} + +static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { + .pin_to_pocctrl = r8a7794_pin_to_pocctrl, +}; + const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", + .ops = &r8a7794_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },