arm64: Add software workaround for Falkor erratum 1041
The ARM architecture defines the memory locations that are permitted to be accessed as the result of a speculative instruction fetch from an exception level for which all stages of translation are disabled. Specifically, the core is permitted to speculatively fetch from the 4KB region containing the current program counter 4K and next 4K. When translation is changed from enabled to disabled for the running exception level (SCTLR_ELn[M] changed from a value of 1 to 0), the Falkor core may errantly speculatively access memory locations outside of the 4KB region permitted by the architecture. The errant memory access may lead to one of the following unexpected behaviors. 1) A System Error Interrupt (SEI) being raised by the Falkor core due to the errant memory access attempting to access a region of memory that is protected by a slave-side memory protection unit. 2) Unpredictable device behavior due to a speculative read from device memory. This behavior may only occur if the instruction cache is disabled prior to or coincident with translation being changed from enabled to disabled. The conditions leading to this erratum will not occur when either of the following occur: 1) A higher exception level disables translation of a lower exception level (e.g. EL2 changing SCTLR_EL1[M] from a value of 1 to 0). 2) An exception level disabling its stage-1 translation if its stage-2 translation is enabled (e.g. EL1 changing SCTLR_EL1[M] from a value of 1 to 0 when HCR_EL2[VM] has a value of 1). To avoid the errant behavior, software must execute an ISB immediately prior to executing the MSR that will change SCTLR_ELn[M] from 1 to 0. Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -75,3 +75,4 @@ stable kernels.
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| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
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| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
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| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
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| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
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@ -550,7 +550,6 @@ config QCOM_QDF2400_ERRATUM_0065
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If unsure, say Y.
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config SOCIONEXT_SYNQUACER_PREITS
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bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
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default y
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@ -569,6 +568,17 @@ config HISILICON_ERRATUM_161600802
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a 128kB offset to be applied to the target address in this commands.
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If unsure, say Y.
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config QCOM_FALKOR_ERRATUM_E1041
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bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
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default y
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help
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Falkor CPU may speculatively fetch instructions from an improper
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memory location when MMU translation is changed from SCTLR_ELn[M]=1
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to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
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If unsure, say Y.
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endmenu
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@ -523,4 +523,14 @@ alternative_endif
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#endif
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.endm
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/**
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* Errata workaround prior to disable MMU. Insert an ISB immediately prior
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* to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
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*/
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.macro pre_disable_mmu_workaround
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#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
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isb
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#endif
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.endm
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#endif /* __ASM_ASSEMBLER_H */
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@ -37,6 +37,7 @@ ENTRY(__cpu_soft_restart)
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mrs x12, sctlr_el1
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ldr x13, =SCTLR_ELx_FLAGS
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bic x12, x12, x13
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pre_disable_mmu_workaround
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msr sctlr_el1, x12
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isb
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@ -96,6 +96,7 @@ ENTRY(entry)
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mrs x0, sctlr_el2
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bic x0, x0, #1 << 0 // clear SCTLR.M
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bic x0, x0, #1 << 2 // clear SCTLR.C
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pre_disable_mmu_workaround
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msr sctlr_el2, x0
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isb
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b 2f
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@ -103,6 +104,7 @@ ENTRY(entry)
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 0 // clear SCTLR.M
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bic x0, x0, #1 << 2 // clear SCTLR.C
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pre_disable_mmu_workaround
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msr sctlr_el1, x0
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isb
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2:
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@ -849,6 +849,7 @@ __primary_switch:
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* to take into account by discarding the current kernel mapping and
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* creating a new one.
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*/
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pre_disable_mmu_workaround
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msr sctlr_el1, x20 // disable the MMU
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isb
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bl __create_page_tables // recreate kernel mapping
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@ -45,6 +45,7 @@ ENTRY(arm64_relocate_new_kernel)
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mrs x0, sctlr_el2
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ldr x1, =SCTLR_ELx_FLAGS
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bic x0, x0, x1
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pre_disable_mmu_workaround
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msr sctlr_el2, x0
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isb
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1:
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@ -153,6 +153,7 @@ reset:
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mrs x5, sctlr_el2
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ldr x6, =SCTLR_ELx_FLAGS
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bic x5, x5, x6 // Clear SCTL_M and etc
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pre_disable_mmu_workaround
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msr sctlr_el2, x5
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isb
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