spi: dw-mid: split rx and tx callbacks when DMA
Currently driver wouldn't work properly if user asked for simplex transfer. The patch separates DMA rx and tx callbacks and finishes transfer correctly in any case. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -26,6 +26,9 @@
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#include <linux/intel_mid_dma.h>
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#include <linux/intel_mid_dma.h>
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#include <linux/pci.h>
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#include <linux/pci.h>
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#define RX_BUSY 0
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#define TX_BUSY 1
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struct mid_dma {
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struct mid_dma {
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struct intel_mid_dma_slave dmas_tx;
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struct intel_mid_dma_slave dmas_tx;
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struct intel_mid_dma_slave dmas_rx;
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struct intel_mid_dma_slave dmas_rx;
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@ -98,15 +101,14 @@ static void mid_spi_dma_exit(struct dw_spi *dws)
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}
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}
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/*
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/*
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* dws->dma_chan_done is cleared before the dma transfer starts,
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* dws->dma_chan_busy is set before the dma transfer starts, callback for tx
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* callback for rx/tx channel will each increment it by 1.
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* channel will clear a corresponding bit.
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* Reaching 2 means the whole spi transaction is done.
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*/
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*/
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static void dw_spi_dma_done(void *arg)
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static void dw_spi_dma_tx_done(void *arg)
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{
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{
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struct dw_spi *dws = arg;
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struct dw_spi *dws = arg;
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if (++dws->dma_chan_done != 2)
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if (test_and_clear_bit(TX_BUSY, &dws->dma_chan_busy) & BIT(RX_BUSY))
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return;
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return;
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dw_spi_xfer_done(dws);
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dw_spi_xfer_done(dws);
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}
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}
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@ -116,6 +118,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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struct dma_slave_config txconf;
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struct dma_slave_config txconf;
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struct dma_async_tx_descriptor *txdesc;
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struct dma_async_tx_descriptor *txdesc;
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if (!dws->tx_dma)
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return NULL;
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txconf.direction = DMA_MEM_TO_DEV;
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txconf.direction = DMA_MEM_TO_DEV;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_addr = dws->dma_addr;
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txconf.dst_maxburst = LNW_DMA_MSIZE_16;
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txconf.dst_maxburst = LNW_DMA_MSIZE_16;
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@ -134,17 +139,33 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws)
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1,
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1,
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DMA_MEM_TO_DEV,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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txdesc->callback = dw_spi_dma_done;
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txdesc->callback = dw_spi_dma_tx_done;
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txdesc->callback_param = dws;
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txdesc->callback_param = dws;
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return txdesc;
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return txdesc;
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}
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}
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/*
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* dws->dma_chan_busy is set before the dma transfer starts, callback for rx
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* channel will clear a corresponding bit.
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*/
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static void dw_spi_dma_rx_done(void *arg)
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{
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struct dw_spi *dws = arg;
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if (test_and_clear_bit(RX_BUSY, &dws->dma_chan_busy) & BIT(TX_BUSY))
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return;
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dw_spi_xfer_done(dws);
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}
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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{
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{
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struct dma_slave_config rxconf;
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struct dma_slave_config rxconf;
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struct dma_async_tx_descriptor *rxdesc;
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struct dma_async_tx_descriptor *rxdesc;
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if (!dws->rx_dma)
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return NULL;
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rxconf.direction = DMA_DEV_TO_MEM;
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rxconf.direction = DMA_DEV_TO_MEM;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_addr = dws->dma_addr;
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rxconf.src_maxburst = LNW_DMA_MSIZE_16;
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rxconf.src_maxburst = LNW_DMA_MSIZE_16;
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@ -163,7 +184,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws)
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1,
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1,
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DMA_DEV_TO_MEM,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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rxdesc->callback = dw_spi_dma_done;
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rxdesc->callback = dw_spi_dma_rx_done;
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rxdesc->callback_param = dws;
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rxdesc->callback_param = dws;
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return rxdesc;
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return rxdesc;
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@ -195,8 +216,6 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
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if (cs_change)
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if (cs_change)
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dw_spi_dma_setup(dws);
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dw_spi_dma_setup(dws);
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dws->dma_chan_done = 0;
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/* 2. Prepare the TX dma transfer */
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/* 2. Prepare the TX dma transfer */
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txdesc = dw_spi_dma_prepare_tx(dws);
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txdesc = dw_spi_dma_prepare_tx(dws);
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@ -204,11 +223,17 @@ static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
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rxdesc = dw_spi_dma_prepare_rx(dws);
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rxdesc = dw_spi_dma_prepare_rx(dws);
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/* rx must be started before tx due to spi instinct */
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/* rx must be started before tx due to spi instinct */
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if (rxdesc) {
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set_bit(RX_BUSY, &dws->dma_chan_busy);
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dmaengine_submit(rxdesc);
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dmaengine_submit(rxdesc);
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dma_async_issue_pending(dws->rxchan);
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dma_async_issue_pending(dws->rxchan);
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}
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if (txdesc) {
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set_bit(TX_BUSY, &dws->dma_chan_busy);
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dmaengine_submit(txdesc);
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dmaengine_submit(txdesc);
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dma_async_issue_pending(dws->txchan);
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dma_async_issue_pending(dws->txchan);
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}
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return 0;
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return 0;
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}
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}
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@ -139,7 +139,7 @@ struct dw_spi {
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struct scatterlist tx_sgl;
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struct scatterlist tx_sgl;
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struct dma_chan *rxchan;
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struct dma_chan *rxchan;
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struct scatterlist rx_sgl;
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struct scatterlist rx_sgl;
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int dma_chan_done;
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unsigned long dma_chan_busy;
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struct device *dma_dev;
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struct device *dma_dev;
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dma_addr_t dma_addr; /* phy address of the Data register */
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dma_addr_t dma_addr; /* phy address of the Data register */
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struct dw_spi_dma_ops *dma_ops;
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struct dw_spi_dma_ops *dma_ops;
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