r6040: define and use bits of register PHY_CC
Define and use the bits of the PHY_CC (status change configuration) register. Signed-off-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -128,6 +128,9 @@
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#define MID_3M 0x82 /* MID3 Medium */
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#define MID_3H 0x84 /* MID3 High */
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#define PHY_CC 0x88 /* PHY status change configuration register */
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#define SCEN 0x8000 /* PHY status change enable */
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#define PHYAD_SHIFT 8 /* PHY address shift */
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#define TMRDIV_SHIFT 0 /* Timer divider shift */
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#define PHY_ST 0x8A /* PHY status register */
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#define MAC_SM 0xAC /* MAC status machine */
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#define MAC_SM_RST 0x0002 /* MAC status machine reset */
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@ -1132,10 +1135,15 @@ static int __devinit r6040_init_one(struct pci_dev *pdev,
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err = -EIO;
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goto err_out_free_res;
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}
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/* If PHY status change register is still set to zero it means the
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* bootloader didn't initialize it */
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* bootloader didn't initialize it, so we set it to:
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* - enable phy status change
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* - enable all phy addresses
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* - set to lowest timer divider */
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if (ioread16(ioaddr + PHY_CC) == 0)
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iowrite16(0x9f07, ioaddr + PHY_CC);
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iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
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7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
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/* Init system & device */
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lp->base = ioaddr;
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