clk: tegra114: implement wait_for_reset and disable_clock for tegra_cpu_car_ops
The conventional CPU hotplug sequence on the other Tegra chips, we will also clock gate the CPU in tegra_cpu_kill() after the CPU was power gated. For Tegra114, the flow controller will clock gate the CPU after the power down sequence. But we still need to implement a empty function for disable_clock to avoid kernel warning message. Signed-off-by: Joseph Lo <josephl@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -250,6 +250,9 @@
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#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
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#define CLK_SOURCE_XUSB_DEV_SRC 0x60c
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#define CLK_SOURCE_EMC 0x19c
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#define CLK_SOURCE_EMC 0x19c
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/* Tegra CPU clock and reset control regs */
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#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
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static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
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static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
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static void __iomem *clk_base;
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static void __iomem *clk_base;
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@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
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}
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}
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}
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}
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static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
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/* Tegra114 CPU clock and reset control functions */
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static void tegra114_wait_cpu_in_reset(u32 cpu)
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{
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unsigned int reg;
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do {
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reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
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cpu_relax();
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} while (!(reg & (1 << cpu))); /* check CPU been reset or not */
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}
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static void tegra114_disable_cpu_clock(u32 cpu)
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{
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/* flow controller would take care in the power sequence. */
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}
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static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
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.wait_for_reset = tegra114_wait_cpu_in_reset,
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.disable_clock = tegra114_disable_cpu_clock,
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};
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static const struct of_device_id pmc_match[] __initconst = {
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static const struct of_device_id pmc_match[] __initconst = {
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{ .compatible = "nvidia,tegra114-pmc" },
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{ .compatible = "nvidia,tegra114-pmc" },
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