drm/nouveau: enable the ttm dma pool when swiotlb is active V3
If the card is capable of more than 32-bit, then use the default TTM page pool code which allocates from anywhere in the memory. Note: If the 'ttm.no_dma' parameter is set, the override is ignored and the default TTM pool is used. V2 use pci_set_consistent_dma_mask V3 Rebase on top of no memory account changes (where/when is my delorean when i need it ?) CC: Ben Skeggs <bskeggs@redhat.com> CC: Francisco Jerez <currojerez@riseup.net> CC: Dave Airlie <airlied@redhat.com> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
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c52494f695
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@ -1049,10 +1049,79 @@ nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
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nouveau_fence_unref(&old_fence);
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}
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static int
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nouveau_ttm_tt_populate(struct ttm_tt *ttm)
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{
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struct drm_nouveau_private *dev_priv;
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struct drm_device *dev;
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unsigned i;
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int r;
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if (ttm->state != tt_unpopulated)
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return 0;
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dev_priv = nouveau_bdev(ttm->bdev);
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dev = dev_priv->dev;
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#ifdef CONFIG_SWIOTLB
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if (swiotlb_nr_tbl()) {
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return ttm_dma_populate(ttm, dev->dev);
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}
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#endif
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r = ttm_pool_populate(ttm);
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if (r) {
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return r;
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}
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for (i = 0; i < ttm->num_pages; i++) {
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ttm->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
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0, PAGE_SIZE,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev, ttm->dma_address[i])) {
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while (--i) {
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pci_unmap_page(dev->pdev, ttm->dma_address[i],
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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ttm->dma_address[i] = 0;
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}
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ttm_pool_unpopulate(ttm);
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return -EFAULT;
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}
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}
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return 0;
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}
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static void
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nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
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{
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struct drm_nouveau_private *dev_priv;
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struct drm_device *dev;
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unsigned i;
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dev_priv = nouveau_bdev(ttm->bdev);
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dev = dev_priv->dev;
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#ifdef CONFIG_SWIOTLB
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if (swiotlb_nr_tbl()) {
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ttm_dma_unpopulate(ttm, dev->dev);
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return;
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}
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#endif
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for (i = 0; i < ttm->num_pages; i++) {
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if (ttm->dma_address[i]) {
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pci_unmap_page(dev->pdev, ttm->dma_address[i],
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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}
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}
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ttm_pool_unpopulate(ttm);
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}
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struct ttm_bo_driver nouveau_bo_driver = {
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.ttm_tt_create = &nouveau_ttm_tt_create,
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.ttm_tt_populate = &ttm_pool_populate,
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.ttm_tt_unpopulate = &ttm_pool_unpopulate,
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.ttm_tt_populate = &nouveau_ttm_tt_populate,
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.ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
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.invalidate_caches = nouveau_bo_invalidate_caches,
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.init_mem_type = nouveau_bo_init_mem_type,
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.evict_flags = nouveau_bo_evict_flags,
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@ -178,6 +178,7 @@ static struct drm_info_list nouveau_debugfs_list[] = {
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{ "memory", nouveau_debugfs_memory_info, 0, NULL },
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{ "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL },
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{ "ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL },
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{ "ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL },
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};
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#define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list)
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@ -407,6 +407,12 @@ nouveau_mem_vram_init(struct drm_device *dev)
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ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
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if (ret)
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return ret;
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ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
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if (ret) {
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/* Reset to default value. */
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pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
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}
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ret = nouveau_ttm_global_init(dev_priv);
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if (ret)
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@ -13,41 +13,6 @@ struct nouveau_sgdma_be {
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u64 offset;
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};
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static int
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nouveau_sgdma_dma_map(struct ttm_tt *ttm)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
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struct drm_device *dev = nvbe->dev;
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int i;
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for (i = 0; i < ttm->num_pages; i++) {
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ttm->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
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0, PAGE_SIZE,
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PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(dev->pdev, ttm->dma_address[i])) {
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return -EFAULT;
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}
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}
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return 0;
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}
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static void
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nouveau_sgdma_dma_unmap(struct ttm_tt *ttm)
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{
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struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm;
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struct drm_device *dev = nvbe->dev;
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int i;
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for (i = 0; i < ttm->num_pages; i++) {
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if (ttm->dma_address[i]) {
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pci_unmap_page(dev->pdev, ttm->dma_address[i],
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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}
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ttm->dma_address[i] = 0;
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}
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}
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static void
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nouveau_sgdma_destroy(struct ttm_tt *ttm)
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{
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@ -67,13 +32,8 @@ nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
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unsigned i, j, pte;
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int r;
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NV_DEBUG(dev, "pg=0x%lx\n", mem->start);
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r = nouveau_sgdma_dma_map(ttm);
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if (r) {
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return r;
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}
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nvbe->offset = mem->start << PAGE_SHIFT;
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pte = (nvbe->offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
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nv_wo32(gpuobj, (pte * 4) + 0, 0x00000000);
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}
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nouveau_sgdma_dma_unmap(ttm);
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return 0;
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}
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@ -141,13 +100,8 @@ nv41_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
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dma_addr_t *list = ttm->dma_address;
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u32 pte = mem->start << 2;
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u32 cnt = ttm->num_pages;
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int r;
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nvbe->offset = mem->start << PAGE_SHIFT;
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r = nouveau_sgdma_dma_map(ttm);
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if (r) {
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return r;
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}
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while (cnt--) {
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nv_wo32(pgt, pte, (*list++ >> 7) | 1);
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}
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nv41_sgdma_flush(nvbe);
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nouveau_sgdma_dma_unmap(ttm);
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return 0;
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}
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@ -256,13 +209,9 @@ nv44_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
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dma_addr_t *list = ttm->dma_address;
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u32 pte = mem->start << 2, tmp[4];
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u32 cnt = ttm->num_pages;
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int i, r;
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int i;
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nvbe->offset = mem->start << PAGE_SHIFT;
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r = nouveau_sgdma_dma_map(ttm);
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if (r) {
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return r;
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}
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if (pte & 0x0000000c) {
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u32 max = 4 - ((pte >> 2) & 0x3);
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nv44_sgdma_fill(pgt, NULL, pte, cnt);
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nv44_sgdma_flush(ttm);
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nouveau_sgdma_dma_unmap(ttm);
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return 0;
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}
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nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
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{
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struct nouveau_mem *node = mem->mm_node;
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int r;
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/* noop: bound in move_notify() */
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r = nouveau_sgdma_dma_map(ttm);
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if (r) {
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return r;
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}
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node->pages = ttm->dma_address;
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return 0;
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}
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nv50_sgdma_unbind(struct ttm_tt *ttm)
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{
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/* noop: unbound in move_notify() */
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nouveau_sgdma_dma_unmap(ttm);
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return 0;
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}
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