MIPS: Netlogic: Use chip_data for irq_chip methods
Update mips/netlogic/common/irq.c and mips/pci/msi-xlp.c to use chip_data to store interrupt controller data pointer. It uses handler_data now, and that causes errors when an API (like the GPIO subsystem) tries to use the handler data. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10817/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -87,7 +87,7 @@ struct nlm_pic_irq {
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static void xlp_pic_enable(struct irq_data *d)
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{
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unsigned long flags;
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
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BUG_ON(!pd);
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spin_lock_irqsave(&pd->node->piclock, flags);
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@ -97,7 +97,7 @@ static void xlp_pic_enable(struct irq_data *d)
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static void xlp_pic_disable(struct irq_data *d)
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{
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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BUG_ON(!pd);
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@ -108,7 +108,7 @@ static void xlp_pic_disable(struct irq_data *d)
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static void xlp_pic_mask_ack(struct irq_data *d)
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{
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
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clear_c0_eimr(pd->picirq);
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ack_c0_eirr(pd->picirq);
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@ -116,7 +116,7 @@ static void xlp_pic_mask_ack(struct irq_data *d)
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static void xlp_pic_unmask(struct irq_data *d)
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{
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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struct nlm_pic_irq *pd = irq_data_get_irq_chip_data(d);
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BUG_ON(!pd);
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@ -193,7 +193,7 @@ void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
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pic_data->picirq = picirq;
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pic_data->node = nlm_get_node(node);
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irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq);
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irq_set_handler_data(xirq, pic_data);
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irq_set_chip_data(xirq, pic_data);
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}
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void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
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@ -202,7 +202,7 @@ void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
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int xirq;
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xirq = nlm_irq_to_xirq(node, irq);
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pic_data = irq_get_handler_data(xirq);
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pic_data = irq_get_chip_data(xirq);
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if (WARN_ON(!pic_data))
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return;
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pic_data->extra_ack = xack;
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@ -131,7 +131,7 @@ struct xlp_msi_data {
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*/
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static void xlp_msi_enable(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
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struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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int vec;
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@ -148,7 +148,7 @@ static void xlp_msi_enable(struct irq_data *d)
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static void xlp_msi_disable(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
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struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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int vec;
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@ -165,7 +165,7 @@ static void xlp_msi_disable(struct irq_data *d)
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static void xlp_msi_mask_ack(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_handler_data(d);
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struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
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int link, vec;
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link = nlm_irq_msilink(d->irq);
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@ -211,7 +211,7 @@ static void xlp_msix_mask_ack(struct irq_data *d)
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msixvec = nlm_irq_msixvec(d->irq);
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link = nlm_irq_msixlink(msixvec);
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pci_msi_mask_irq(d);
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md = irq_data_get_irq_handler_data(d);
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md = irq_data_get_irq_chip_data(d);
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/* Ack MSI on bridge */
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if (cpu_is_xlp9xx()) {
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@ -302,7 +302,7 @@ static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
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/* Get MSI data for the link */
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lirq = PIC_PCIE_LINK_MSI_IRQ(link);
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xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
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md = irq_get_handler_data(xirq);
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md = irq_get_chip_data(xirq);
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msiaddr = MSI_LINK_ADDR(node, link);
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spin_lock_irqsave(&md->msi_lock, flags);
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@ -409,7 +409,7 @@ static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
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/* Get MSI data for the link */
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lirq = PIC_PCIE_MSIX_IRQ(link);
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xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
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md = irq_get_handler_data(xirq);
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md = irq_get_chip_data(xirq);
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msixaddr = MSIX_LINK_ADDR(node, link);
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spin_lock_irqsave(&md->msi_lock, flags);
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@ -485,7 +485,7 @@ void __init xlp_init_node_msi_irqs(int node, int link)
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irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
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for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
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irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
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irq_set_handler_data(i, md);
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irq_set_chip_data(i, md);
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}
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for (i = 0; i < XLP_MSIXVEC_PER_LINK ; i++) {
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@ -508,7 +508,7 @@ void __init xlp_init_node_msi_irqs(int node, int link)
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/* Initialize MSI-X extended irq space for the link */
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irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
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irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
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irq_set_handler_data(irq, md);
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irq_set_chip_data(irq, md);
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}
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}
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@ -520,7 +520,7 @@ void nlm_dispatch_msi(int node, int lirq)
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link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
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irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
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md = irq_get_handler_data(irqbase);
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md = irq_get_chip_data(irqbase);
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if (cpu_is_xlp9xx())
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status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
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md->msi_enabled_mask;
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@ -550,7 +550,7 @@ void nlm_dispatch_msix(int node, int lirq)
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link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
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irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
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md = irq_get_handler_data(irqbase);
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md = irq_get_chip_data(irqbase);
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if (cpu_is_xlp9xx())
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status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
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else
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