It contains the imx device tree updates for 3.12.
- New pinctrl entry additions for various peripherals - Devices enabling for imx6, imx5 and imx27 boards - Add missing device nodes like iim, owire, audmux and sram, etc. - Various updates on boards like phytec, wandboard and sabresd - Consolidate pad macros between imx6q and imx6dl -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJSFjFkAAoJEFBXWFqHsHzOjkcH/3c2IqXrZ/1GAQ8r4fkN1D7h eOOiQ8hZriBxgbw72xeYAHTeMx3xZphW9n+fLHjrtqJNDI4yz/XWn2mdf55fFanm jQb6bssbRHG4VgHaMuEjzKK4zQDrlSZgcVkOT2Aj0y+Mg7L21xUh9zRW3p2xh33x Cg1NDLzFDChQBK/IIA0sHVOtmgn7lflfwlBbR2zvSHE4U4HNheqMCuxb3gB3aWXZ VdxDbzQUukIwHrNlTTIV2CN2UOXfUi1Xgk7Xd/PvfAyywWpQnr7KMl9RdK4pxGo9 6G+Y984sh92jf43cF3uSCWN3+Y1bEQwmfQThoJCDV7sATG6yqblyo2X/cmUwK/c= =llVa -----END PGP SIGNATURE----- Merge tag 'imx-dt-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc From Shawn Guo: It contains the imx device tree updates for 3.12. - New pinctrl entry additions for various peripherals - Devices enabling for imx6, imx5 and imx27 boards - Add missing device nodes like iim, owire, audmux and sram, etc. - Various updates on boards like phytec, wandboard and sabresd - Consolidate pad macros between imx6q and imx6dl * tag 'imx-dt-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: (92 commits) ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ARM: dts: i.MX27: Increase "clock-latency" value ARM: dts: i.MX27: Add label to CPU node ARM: dts: i.MX27: Remove optional "ptp" clock source for FEC ... Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
commit
334b0f0913
|
@ -197,6 +197,7 @@ clocks and IDs.
|
|||
spdif0_gate 183
|
||||
spdif1_gate 184
|
||||
spdif_ipg_gate 185
|
||||
ocram 186
|
||||
|
||||
Examples (for mx53):
|
||||
|
||||
|
|
|
@ -113,6 +113,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx27-pdk.dtb \
|
||||
imx27-phytec-phycore-som.dtb \
|
||||
imx27-phytec-phycore-rdk.dtb \
|
||||
imx27-phytec-phycard-s-som.dtb \
|
||||
imx27-phytec-phycard-s-rdk.dtb \
|
||||
imx31-bug.dtb \
|
||||
imx51-apf51.dtb \
|
||||
imx51-apf51dev.dtb \
|
||||
|
@ -132,6 +134,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
|
|||
imx6q-sabrelite.dtb \
|
||||
imx6q-sabresd.dtb \
|
||||
imx6q-sbc6x.dtb \
|
||||
imx6q-wandboard.dtb \
|
||||
imx6sl-evk.dtb \
|
||||
vf610-twr.dtb
|
||||
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
|
||||
|
|
|
@ -13,19 +13,35 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
spi0 = &spi1;
|
||||
spi1 = &spi2;
|
||||
spi2 = &spi3;
|
||||
usb0 = &usbotg;
|
||||
usb1 = &usbhost1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
asic: asic-interrupt-controller@68000000 {
|
||||
compatible = "fsl,imx25-asic", "fsl,avic";
|
||||
interrupt-controller;
|
||||
|
@ -377,7 +393,8 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdc@53fbc000 {
|
||||
lcdc: lcdc@53fbc000 {
|
||||
compatible = "fsl,imx25-fb", "fsl,imx21-fb";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
interrupts = <39>;
|
||||
clocks = <&clks 103>, <&clks 66>, <&clks 49>;
|
||||
|
@ -424,6 +441,7 @@
|
|||
reg = <0x53fd4000 0x4000>;
|
||||
clocks = <&clks 112>, <&clks 68>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
interrupts = <34>;
|
||||
};
|
||||
|
||||
|
@ -444,6 +462,13 @@
|
|||
interrupts = <26>;
|
||||
};
|
||||
|
||||
iim: iim@53ff0000 {
|
||||
compatible = "fsl,imx25-iim", "fsl,imx27-iim";
|
||||
reg = <0x53ff0000 0x4000>;
|
||||
interrupts = <19>;
|
||||
clocks = <&clks 99>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@1 {
|
||||
compatible = "nop-usbphy";
|
||||
status = "disabled";
|
||||
|
|
|
@ -53,6 +53,11 @@
|
|||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1374";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
|
|
93
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
Normal file
93
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
Normal file
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Copyright 2012 Markus Pargmann, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include "imx27-phytec-phycard-s-som.dts"
|
||||
|
||||
/ {
|
||||
model = "Phytec pca100 rapid development kit";
|
||||
compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
|
||||
|
||||
display: display {
|
||||
model = "Primeview-PD050VL1";
|
||||
native-mode = <&timing0>;
|
||||
bits-per-pixel = <16>; /* non-standard but required */
|
||||
fsl,pcr = <0xf0c88080>; /* non-standard but required */
|
||||
display-timings {
|
||||
timing0: 640x480 {
|
||||
hactive = <640>;
|
||||
vactive = <480>;
|
||||
hback-porch = <112>;
|
||||
hfront-porch = <36>;
|
||||
hsync-len = <32>;
|
||||
vback-porch = <33>;
|
||||
vfront-porch = <33>;
|
||||
vsync-len = <2>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_3v3: 3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fb {
|
||||
display = <&display>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
adc@64 {
|
||||
compatible = "maxim,max1037";
|
||||
vcc-supply = <®_3v3>;
|
||||
reg = <0x64>;
|
||||
};
|
||||
};
|
||||
|
||||
&owire {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci2 {
|
||||
cd-gpios = <&gpio3 29 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
44
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
Normal file
44
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
Normal file
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
|
||||
* and Markus Pargmann, Pengutronix
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "imx27.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Phytec pca100";
|
||||
compatible = "phytec,imx27-pca100", "fsl,imx27";
|
||||
|
||||
memory {
|
||||
reg = <0xa0000000 0x08000000>; /* 128MB */
|
||||
};
|
||||
};
|
||||
|
||||
&cspi1 {
|
||||
fsl,spi-num-chipselects = <2>;
|
||||
cs-gpios = <&gpio4 28 0>,
|
||||
<&gpio4 27 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
|
||||
at24@52 {
|
||||
compatible = "at,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
};
|
||||
};
|
|
@ -35,3 +35,16 @@
|
|||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&weim {
|
||||
can@d4000000 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <4 0x00000000 0x00000100>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <19 0x2>;
|
||||
nxp,external-clock-frequency = <16000000>;
|
||||
nxp,tx-output-config = <0x16>;
|
||||
nxp,no-comparator-bypass;
|
||||
fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -17,49 +17,22 @@
|
|||
compatible = "phytec,imx27-pcm038", "fsl,imx27";
|
||||
|
||||
memory {
|
||||
reg = <0x0 0x0>;
|
||||
reg = <0xa0000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
status = "okay";
|
||||
|
||||
/* SSI0 <=> PINS_4 (MC13783 Audio) */
|
||||
ssi0 {
|
||||
fsl,audmux-port = <0>;
|
||||
fsl,port-config = <0xcb205000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
aipi@10000000 { /* aipi1 */
|
||||
serial@1000a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@1001d000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
at24@52 {
|
||||
compatible = "at,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
};
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
lm75@4a {
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aipi@10020000 { /* aipi2 */
|
||||
ethernet@1002b000 {
|
||||
phy-reset-gpios = <&gpio3 30 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
nor_flash@c0000000 {
|
||||
compatible = "cfi-flash";
|
||||
bank-width = <2>;
|
||||
reg = <0xc0000000 0x02000000>;
|
||||
linux,mtd-name = "physmap-flash.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
pins4 {
|
||||
fsl,audmux-port = <2>;
|
||||
fsl,port-config = <0x00001000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -80,28 +53,16 @@
|
|||
fsl,mc13xxx-uses-rtc;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1a {
|
||||
/* SW1A and SW1B joined operation */
|
||||
sw1_reg: sw1a {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1520000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw1b_reg: sw1b {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw2a_reg: sw2a {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
sw2b_reg: sw2b {
|
||||
/* SW2A and SW2B joined operation */
|
||||
sw2_reg: sw2a {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
|
@ -172,8 +133,62 @@
|
|||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
phy-reset-gpios = <&gpio3 30 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
at24@52 {
|
||||
compatible = "at,24c32";
|
||||
pagesize = <32>;
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
lm75@4a {
|
||||
compatible = "national,lm75";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
|
||||
&nfc {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&weim {
|
||||
status = "okay";
|
||||
|
||||
nor: nor@c0000000 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x00000000 0x02000000>;
|
||||
bank-width = <2>;
|
||||
linux,mtd-name = "physmap-flash.0";
|
||||
fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
sram: sram@c8000000 {
|
||||
compatible = "mtd-ram";
|
||||
reg = <1 0x00000000 0x00800000>;
|
||||
bank-width = <2>;
|
||||
linux,mtd-name = "mtd-ram.0";
|
||||
fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -13,25 +13,27 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
spi0 = &cspi1;
|
||||
spi1 = &cspi2;
|
||||
spi2 = &cspi3;
|
||||
};
|
||||
|
||||
avic: avic-interrupt-controller@e0000000 {
|
||||
compatible = "fsl,imx27-avic", "fsl,avic";
|
||||
aitc: aitc-interrupt-controller@e0000000 {
|
||||
compatible = "fsl,imx27-aitc", "fsl,avic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x10040000 0x1000>;
|
||||
|
@ -47,11 +49,29 @@
|
|||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
|
||||
cpu: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,arm926ej-s";
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
266000 1300000
|
||||
399000 1450000
|
||||
>;
|
||||
clock-latency = <62500>;
|
||||
clocks = <&clks 18>;
|
||||
voltage-tolerance = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&avic>;
|
||||
interrupt-parent = <&aitc>;
|
||||
ranges;
|
||||
|
||||
aipi@10000000 { /* AIPI1 */
|
||||
|
@ -75,7 +95,7 @@
|
|||
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x10002000 0x1000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&clks 0>;
|
||||
clocks = <&clks 74>;
|
||||
};
|
||||
|
||||
gpt1: timer@10003000 {
|
||||
|
@ -102,7 +122,7 @@
|
|||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm0: pwm@10006000 {
|
||||
pwm: pwm@10006000 {
|
||||
compatible = "fsl,imx27-pwm";
|
||||
reg = <0x10006000 0x1000>;
|
||||
interrupts = <23>;
|
||||
|
@ -110,6 +130,21 @@
|
|||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
kpp: kpp@10008000 {
|
||||
compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
|
||||
reg = <0x10008000 0x1000>;
|
||||
interrupts = <21>;
|
||||
clocks = <&clks 37>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
owire: owire@10009000 {
|
||||
compatible = "fsl,imx27-owire", "fsl,imx21-owire";
|
||||
reg = <0x10009000 0x1000>;
|
||||
clocks = <&clks 35>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@1000a000 {
|
||||
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
|
||||
reg = <0x1000a000 0x1000>;
|
||||
|
@ -260,6 +295,14 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
audmux: audmux@10016000 {
|
||||
compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
|
||||
reg = <0x10016000 0x1000>;
|
||||
clocks = <&clks 0>;
|
||||
clock-names = "audmux";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cspi3: cspi@10017000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -342,6 +385,15 @@
|
|||
reg = <0x10020000 0x20000>;
|
||||
ranges;
|
||||
|
||||
fb: fb@10021000 {
|
||||
compatible = "fsl,imx27-fb", "fsl,imx21-fb";
|
||||
interrupts = <61>;
|
||||
reg = <0x10021000 0x1000>;
|
||||
clocks = <&clks 36>, <&clks 65>, <&clks 59>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
coda: coda@10023000 {
|
||||
compatible = "fsl,imx27-vpu";
|
||||
reg = <0x10023000 0x0200>;
|
||||
|
@ -351,27 +403,37 @@
|
|||
iram = <&iram>;
|
||||
};
|
||||
|
||||
sahara2: sahara@10025000 {
|
||||
compatible = "fsl,imx27-sahara";
|
||||
reg = <0x10025000 0x1000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks 32>, <&clks 64>;
|
||||
clock-names = "ipg", "ahb";
|
||||
};
|
||||
|
||||
clks: ccm@10027000{
|
||||
compatible = "fsl,imx27-ccm";
|
||||
reg = <0x10027000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
iim: iim@10028000 {
|
||||
compatible = "fsl,imx27-iim";
|
||||
reg = <0x10028000 0x1000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks 38>;
|
||||
};
|
||||
|
||||
fec: ethernet@1002b000 {
|
||||
compatible = "fsl,imx27-fec";
|
||||
reg = <0x1002b000 0x4000>;
|
||||
interrupts = <50>;
|
||||
clocks = <&clks 48>, <&clks 67>, <&clks 0>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
clocks = <&clks 48>, <&clks 67>;
|
||||
clock-names = "ipg", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
iram: iram@ffff4c00 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xffff4c00 0xb400>;
|
||||
};
|
||||
|
||||
nfc: nand@d8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
@ -381,5 +443,27 @@
|
|||
clocks = <&clks 54>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
weim: weim@d8002000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,imx27-weim";
|
||||
reg = <0xd8002000 0x1000>;
|
||||
clocks = <&clks 0>;
|
||||
ranges = <
|
||||
0 0 0xc0000000 0x08000000
|
||||
1 0 0xc8000000 0x08000000
|
||||
2 0 0xd0000000 0x02000000
|
||||
3 0 0xd2000000 0x02000000
|
||||
4 0 0xd4000000 0x02000000
|
||||
5 0 0xd6000000 0x02000000
|
||||
>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
iram: iram@ffff4c00 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xffff4c00 0xb400>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -20,6 +20,16 @@
|
|||
serial4 = &uart5;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm1136";
|
||||
device_type = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
avic: avic-interrupt-controller@60000000 {
|
||||
compatible = "fsl,imx31-avic", "fsl,avic";
|
||||
interrupt-controller;
|
||||
|
@ -94,6 +104,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
iim: iim@5001c000 {
|
||||
compatible = "fsl,imx31-iim", "fsl,imx27-iim";
|
||||
reg = <0x5001c000 0x1000>;
|
||||
interrupts = <19>;
|
||||
clocks = <&clks 25>;
|
||||
};
|
||||
|
||||
clks: ccm@53f80000{
|
||||
compatible = "fsl,imx31-ccm";
|
||||
reg = <0x53f80000 0x4000>;
|
||||
|
|
|
@ -26,10 +26,6 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
ckih1 {
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
clock-frequency = <33554432>;
|
||||
};
|
||||
|
|
|
@ -63,6 +63,10 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
ckih1 {
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
clk_26M: codec_clock {
|
||||
compatible = "fixed-clock";
|
||||
reg=<0>;
|
||||
|
@ -108,6 +112,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,mc13892";
|
||||
spi-max-frequency = <6000000>;
|
||||
spi-cs-high;
|
||||
reg = <0>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <8 0x4>;
|
||||
|
|
|
@ -15,13 +15,18 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
gpio3 = &gpio4;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &cspi;
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@e0000000 {
|
||||
|
@ -42,7 +47,7 @@
|
|||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
clock-frequency = <22579200>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
|
@ -149,6 +154,9 @@
|
|||
reg = <0x70014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 49>;
|
||||
dmas = <&sdma 24 1 0>,
|
||||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
@ -300,275 +308,6 @@
|
|||
iomuxc: iomuxc@73fa8000 {
|
||||
compatible = "fsl,imx51-iomuxc";
|
||||
reg = <0x73fa8000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_2: fecgrp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi2 {
|
||||
pinctrl_ecspi2_1: ecspi2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_2: i2c2grp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp1 {
|
||||
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp2 {
|
||||
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 0x5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pata {
|
||||
pinctrl_pata_1: patagrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
|
||||
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
|
||||
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
|
||||
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
|
||||
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
|
||||
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
|
||||
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
|
||||
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
|
||||
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
|
||||
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
|
||||
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
|
||||
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
|
||||
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
|
||||
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
|
||||
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
|
||||
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
|
||||
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
|
||||
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
|
||||
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
|
||||
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
|
||||
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
|
||||
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
|
||||
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
|
||||
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
|
||||
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
|
||||
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
|
||||
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
|
||||
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
|
||||
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
||||
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
||||
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
||||
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_2: uart3grp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
kpp {
|
||||
pinctrl_kpp_1: kppgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@73fb4000 {
|
||||
|
@ -628,6 +367,13 @@
|
|||
reg = <0x80000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
iim: iim@83f98000 {
|
||||
compatible = "fsl,imx51-iim", "fsl,imx27-iim";
|
||||
reg = <0x83f98000 0x4000>;
|
||||
interrupts = <69>;
|
||||
clocks = <&clks 107>;
|
||||
};
|
||||
|
||||
ecspi2: ecspi@83fac000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -645,6 +391,7 @@
|
|||
interrupts = <6>;
|
||||
clocks = <&clks 56>, <&clks 56>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
|
||||
};
|
||||
|
||||
|
@ -684,6 +431,9 @@
|
|||
reg = <0x83fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 48>;
|
||||
dmas = <&sdma 28 0 0>,
|
||||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
@ -695,6 +445,23 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
weim: weim@83fda000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,imx51-weim";
|
||||
reg = <0x83fda000 0x1000>;
|
||||
clocks = <&clks 57>;
|
||||
ranges = <
|
||||
0 0 0xb0000000 0x08000000
|
||||
1 0 0xb8000000 0x08000000
|
||||
2 0 0xc0000000 0x08000000
|
||||
3 0 0xc8000000 0x04000000
|
||||
4 0 0xcc000000 0x02000000
|
||||
5 0 0xce000000 0x02000000
|
||||
>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nfc: nand@83fdb000 {
|
||||
compatible = "fsl,imx51-nand";
|
||||
reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
|
||||
|
@ -716,6 +483,9 @@
|
|||
reg = <0x83fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks 50>;
|
||||
dmas = <&sdma 46 0 0>,
|
||||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
@ -732,3 +502,319 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmuxgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
|
||||
MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
|
||||
MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
fec {
|
||||
pinctrl_fec_1: fecgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
|
||||
MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
|
||||
MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
|
||||
MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
|
||||
MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
|
||||
MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_2: fecgrp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
|
||||
MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
|
||||
MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
|
||||
MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
|
||||
MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
|
||||
MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
|
||||
MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
|
||||
MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
|
||||
MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
|
||||
MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
|
||||
MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
|
||||
MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
|
||||
MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
|
||||
MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
|
||||
MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
|
||||
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
|
||||
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi2 {
|
||||
pinctrl_ecspi2_1: ecspi2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
|
||||
MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
|
||||
MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc1 {
|
||||
pinctrl_esdhc1_1: esdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
|
||||
MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
|
||||
MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
|
||||
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
|
||||
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
|
||||
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esdhc2 {
|
||||
pinctrl_esdhc2_1: esdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
|
||||
MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
|
||||
MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
|
||||
MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
|
||||
MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
|
||||
MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_2: i2c2grp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_3: i2c2grp-3 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
|
||||
MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp1 {
|
||||
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
|
||||
MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
|
||||
MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
|
||||
MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
|
||||
MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
|
||||
MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
|
||||
MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
|
||||
MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
|
||||
MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
|
||||
MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
|
||||
MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
|
||||
MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
|
||||
MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
|
||||
MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
|
||||
MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
|
||||
MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
|
||||
MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
|
||||
MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
|
||||
MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
|
||||
MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
|
||||
MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
|
||||
MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
|
||||
MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
|
||||
MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
|
||||
MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
|
||||
MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu_disp2 {
|
||||
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
|
||||
MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
|
||||
MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
|
||||
MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
|
||||
MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
|
||||
MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
|
||||
MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
|
||||
MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
|
||||
MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
|
||||
MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
|
||||
MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
|
||||
MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
|
||||
MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
|
||||
MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
|
||||
MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
|
||||
MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
|
||||
MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
|
||||
MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
|
||||
MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
|
||||
MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
kpp {
|
||||
pinctrl_kpp_1: kppgrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
|
||||
MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
|
||||
MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
|
||||
MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
|
||||
MX51_PAD_KEY_COL0__KEY_COL0 0xe8
|
||||
MX51_PAD_KEY_COL1__KEY_COL1 0xe8
|
||||
MX51_PAD_KEY_COL2__KEY_COL2 0xe8
|
||||
MX51_PAD_KEY_COL3__KEY_COL3 0xe8
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pata {
|
||||
pinctrl_pata_1: patagrp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
|
||||
MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
|
||||
MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
|
||||
MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
|
||||
MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
|
||||
MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
|
||||
MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
|
||||
MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
|
||||
MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
|
||||
MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
|
||||
MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
|
||||
MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
|
||||
MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
|
||||
MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
|
||||
MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
|
||||
MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
|
||||
MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
|
||||
MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
|
||||
MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
|
||||
MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
|
||||
MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
|
||||
MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
|
||||
MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
|
||||
MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
|
||||
MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
|
||||
MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
|
||||
MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
|
||||
MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
|
||||
MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
|
||||
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
|
||||
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
|
||||
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
|
||||
MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
|
||||
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
|
||||
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
|
||||
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_2: uart3grp-2 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
|
||||
MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbh1 {
|
||||
pinctrl_usbh1_1: usbh1grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
|
||||
MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
|
||||
MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
|
||||
MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
|
||||
MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
|
||||
MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
|
||||
MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
|
||||
MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
|
||||
MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
|
||||
MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
|
||||
MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
|
||||
MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbh2 {
|
||||
pinctrl_usbh2_1: usbh2grp-1 {
|
||||
fsl,pins = <
|
||||
MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
|
||||
MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
|
||||
MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
|
||||
MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
|
||||
MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
|
||||
MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
|
||||
MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
|
||||
MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
|
||||
MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
|
||||
MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
|
||||
MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
|
||||
MX51_PAD_EIM_A26__USBH2_STP 0x1e5
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -93,6 +93,15 @@
|
|||
regulator-max-microvolt = <3200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_vbus: usb_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio7 8 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
@ -145,6 +154,7 @@
|
|||
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
|
||||
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
|
||||
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
|
||||
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
|
||||
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
|
||||
>;
|
||||
};
|
||||
|
@ -297,8 +307,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
vbus-supply = <®_usb_vbus>;
|
||||
phy_type = "utmi";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
|
|
|
@ -15,11 +15,6 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
|
@ -30,6 +25,24 @@
|
|||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &cspi;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a8";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
tzic: tz-interrupt-controller@0fffc000 {
|
||||
|
@ -140,6 +153,9 @@
|
|||
reg = <0x50014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 49>;
|
||||
dmas = <&sdma 24 1 0>,
|
||||
<&sdma 25 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
@ -957,6 +973,13 @@
|
|||
reg = <0x60000000 0x10000000>;
|
||||
ranges;
|
||||
|
||||
iim: iim@63f98000 {
|
||||
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
|
||||
reg = <0x63f98000 0x4000>;
|
||||
interrupts = <69>;
|
||||
clocks = <&clks 107>;
|
||||
};
|
||||
|
||||
uart5: serial@63f90000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x63f90000 0x4000>;
|
||||
|
@ -990,6 +1013,7 @@
|
|||
interrupts = <6>;
|
||||
clocks = <&clks 56>, <&clks 56>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
|
@ -1029,6 +1053,9 @@
|
|||
reg = <0x63fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 48>;
|
||||
dmas = <&sdma 28 0 0>,
|
||||
<&sdma 29 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
@ -1053,6 +1080,9 @@
|
|||
reg = <0x63fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks 50>;
|
||||
dmas = <&sdma 46 0 0>,
|
||||
<&sdma 47 0 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
@ -1076,6 +1106,22 @@
|
|||
crtcs = <&ipu 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpu: vpu@63ff4000 {
|
||||
compatible = "fsl,imx53-vpu";
|
||||
reg = <0x63ff4000 0x1000>;
|
||||
interrupts = <9>;
|
||||
clocks = <&clks 63>, <&clks 63>;
|
||||
clock-names = "per", "ahb";
|
||||
iram = <&ocram>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ocram: sram@f8000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0xf8000000 0x20000>;
|
||||
clocks = <&clks 186>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -15,25 +15,3 @@
|
|||
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
|
||||
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -15,22 +15,3 @@
|
|||
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
|
||||
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
||||
MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -10,6 +10,7 @@
|
|||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6dl.dtsi"
|
||||
#include "imx6qdl-wandboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Dual Lite Board";
|
||||
|
@ -19,26 +20,3 @@
|
|||
reg = <0x10000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -8,8 +8,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include "imx6qdl.dtsi"
|
||||
#include "imx6dl-pinfunc.h"
|
||||
#include "imx6qdl.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
|
@ -32,238 +32,15 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x20000>;
|
||||
clocks = <&clks 142>;
|
||||
};
|
||||
|
||||
aips1: aips-bus@02000000 {
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6dl-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_2: audmux-2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
|
||||
MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
|
||||
MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
|
||||
MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_2: i2c1grp-2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg {
|
||||
pinctrl_usbotg_2: usbotggrp-2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp_2 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
weim {
|
||||
pinctrl_weim_cs0_1: weim_cs0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_nor_1: weim_norgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
||||
/* data */
|
||||
MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
||||
MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
||||
MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
||||
MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
||||
MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
||||
MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
||||
MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
||||
MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
||||
MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
||||
MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
||||
MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
||||
MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
||||
MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
||||
MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
||||
MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
||||
MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
||||
/* address */
|
||||
MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
||||
MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
||||
MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
||||
MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
||||
MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
||||
MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
||||
MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
||||
MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
||||
MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pxp: pxp@020f0000 {
|
||||
|
@ -294,3 +71,20 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
clocks = <&clks 33>, <&clks 34>,
|
||||
<&clks 39>, <&clks 40>,
|
||||
<&clks 135>, <&clks 136>;
|
||||
clock-names = "di0_pll", "di1_pll",
|
||||
"di0_sel", "di1_sel",
|
||||
"di0", "di1";
|
||||
|
||||
lvds-channel@0 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>;
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -57,7 +57,7 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000
|
||||
MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -65,8 +65,8 @@
|
|||
arm2 {
|
||||
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
|
||||
MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
|
||||
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -97,6 +97,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2_2>;
|
||||
fsl,dte-mode;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_1>;
|
||||
|
|
|
@ -20,6 +20,110 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ecspi3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi3_1>;
|
||||
status = "okay";
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 24 0>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "m25p80";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1_1>;
|
||||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
pmic@58 {
|
||||
compatible = "dialog,da9063";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <17 0x8>; /* active-low GPIO4_17 */
|
||||
|
||||
regulators {
|
||||
vddcore_reg: bcore1 {
|
||||
regulator-min-microvolt = <730000>;
|
||||
regulator-max-microvolt = <1380000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vddsoc_reg: bcore2 {
|
||||
regulator-min-microvolt = <730000>;
|
||||
regulator-max-microvolt = <1380000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_ddr3_reg: bpro {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_3v3_reg: bperi {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_buckmem_reg: bmem {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_eth_reg: bio {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_eth_io_reg: ldo4 {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_mx6_snvs_reg: ldo5 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_3v3_pmic_io_reg: ldo6 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd_sd0_reg: ldo9 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_sd1_reg: ldo10 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_mx6_high_reg: ldo11 {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
@ -27,7 +131,9 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
||||
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
|
||||
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -35,8 +141,8 @@
|
|||
pfla02 {
|
||||
pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
|
||||
MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
|
||||
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -20,24 +20,6 @@
|
|||
compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -65,6 +65,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio3 19 0>;
|
||||
|
@ -91,14 +95,14 @@
|
|||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000
|
||||
MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000
|
||||
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
|
||||
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
||||
MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
|
||||
MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
|
||||
MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
|
||||
MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
|
||||
MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
|
||||
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
||||
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
|
||||
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
@ -163,7 +167,7 @@
|
|||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 169>;
|
||||
clocks = <&clks 201>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
|
|
|
@ -20,21 +20,6 @@
|
|||
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
||||
MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
26
arch/arm/boot/dts/imx6q-wandboard.dts
Normal file
26
arch/arm/boot/dts/imx6q-wandboard.dts
Normal file
|
@ -0,0 +1,26 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "imx6q.dtsi"
|
||||
#include "imx6qdl-wandboard.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Wandboard i.MX6 Quad Board";
|
||||
compatible = "wand,imx6q-wandboard", "fsl,imx6q";
|
||||
|
||||
memory {
|
||||
reg = <0x10000000 0x80000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
|
@ -8,8 +8,8 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include "imx6qdl.dtsi"
|
||||
#include "imx6q-pinfunc.h"
|
||||
#include "imx6qdl.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
|
@ -61,6 +61,12 @@
|
|||
};
|
||||
|
||||
soc {
|
||||
ocram: sram@00900000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x40000>;
|
||||
clocks = <&clks 142>;
|
||||
};
|
||||
|
||||
aips-bus@02000000 { /* AIPS1 */
|
||||
spba-bus@02000000 {
|
||||
ecspi5: ecspi@02018000 {
|
||||
|
@ -77,357 +83,54 @@
|
|||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6q-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
|
||||
/* shared pinctrl settings */
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmux-1 {
|
||||
ipu2 {
|
||||
pinctrl_ipu2_1: ipu2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
|
||||
MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
|
||||
MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
|
||||
MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux_2: audmux-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
|
||||
MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
|
||||
MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
|
||||
MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi3 {
|
||||
pinctrl_ecspi3_1: ecspi3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
||||
MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
||||
MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_3: enetgrp-3 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_2: i2c1grp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
pinctrl_i2c3_1: i2c3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg {
|
||||
pinctrl_usbotg_1: usbotggrp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg_2: usbotggrp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_2: usdhc2grp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_2: usdhc4grp-2 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
weim {
|
||||
pinctrl_weim_cs0_1: weim_cs0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_nor_1: weimnorgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
||||
/* data */
|
||||
MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
||||
MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
||||
MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
||||
MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
||||
MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
||||
MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
||||
MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
||||
MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
||||
MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
||||
MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
||||
MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
||||
MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
||||
MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
||||
MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
||||
MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
||||
MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
||||
/* address */
|
||||
MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
||||
MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
||||
MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
||||
MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
||||
MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
||||
MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
||||
MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
||||
MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
||||
MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sata: sata@02200000 {
|
||||
compatible = "fsl,imx6q-ahci";
|
||||
reg = <0x02200000 0x4000>;
|
||||
interrupts = <0 39 0x04>;
|
||||
clocks = <&clks 154>, <&clks 187>, <&clks 105>;
|
||||
clock-names = "sata", "sata_ref", "ahb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ipu2: ipu@02800000 {
|
||||
#crtc-cells = <1>;
|
||||
compatible = "fsl,imx6q-ipu";
|
||||
|
|
|
@ -45,6 +45,28 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
||||
MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4_1>;
|
||||
|
|
|
@ -27,6 +27,15 @@
|
|||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usb_h1_vbus: usb_h1_vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_h1_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 29 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_audio: wm8962_supply {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wm8962-supply";
|
||||
|
@ -41,12 +50,14 @@
|
|||
volume-up {
|
||||
label = "Volume Up";
|
||||
gpios = <&gpio1 4 0>;
|
||||
gpio-key,wakeup;
|
||||
linux,code = <115>; /* KEY_VOLUMEUP */
|
||||
};
|
||||
|
||||
volume-down {
|
||||
label = "Volume Down";
|
||||
gpios = <&gpio1 5 0>;
|
||||
gpio-key,wakeup;
|
||||
linux,code = <114>; /* KEY_VOLUMEDOWN */
|
||||
};
|
||||
};
|
||||
|
@ -77,6 +88,22 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
fsl,spi-num-chipselects = <1>;
|
||||
cs-gpios = <&gpio4 9 0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1_2>;
|
||||
status = "okay";
|
||||
|
||||
flash: m25p80@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p32";
|
||||
spi-max-frequency = <20000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
|
@ -93,7 +120,7 @@
|
|||
codec: wm8962@1a {
|
||||
compatible = "wlf,wm8962";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clks 169>;
|
||||
clocks = <&clks 201>;
|
||||
DCVDD-supply = <®_audio>;
|
||||
DBVDD-supply = <®_audio>;
|
||||
AVDD-supply = <®_audio>;
|
||||
|
@ -113,6 +140,68 @@
|
|||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3_2>;
|
||||
status = "okay";
|
||||
|
||||
egalax_ts@04 {
|
||||
compatible = "eeti,egalax_ts";
|
||||
reg = <0x04>;
|
||||
interrupt-parent = <&gpio6>;
|
||||
interrupts = <7 2>;
|
||||
wakeup-gpios = <&gpio6 7 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
|
||||
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
|
||||
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
||||
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
||||
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
||||
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
|
||||
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
|
||||
lvds-channel@1 {
|
||||
fsl,data-mapping = "spwg";
|
||||
fsl,data-width = <18>;
|
||||
status = "okay";
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: hsd100pxn1 {
|
||||
clock-frequency = <65000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <768>;
|
||||
hback-porch = <220>;
|
||||
hfront-porch = <40>;
|
||||
vback-porch = <21>;
|
||||
vfront-porch = <7>;
|
||||
hsync-len = <60>;
|
||||
vsync-len = <10>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssi2 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
|
@ -125,6 +214,7 @@
|
|||
};
|
||||
|
||||
&usbh1 {
|
||||
vbus-supply = <®_usb_h1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
137
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
Normal file
137
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
Normal file
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
|
||||
reg_2p5v: 2p5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "2P5V";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: 3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6-wandboard-sgtl5000",
|
||||
"fsl,imx-audio-sgtl5000";
|
||||
model = "imx6-wandboard-sgtl5000";
|
||||
ssi-controller = <&ssi1>;
|
||||
audio-codec = <&codec>;
|
||||
audio-routing =
|
||||
"MIC_IN", "Mic Jack",
|
||||
"Mic Jack", "Mic Bias",
|
||||
"Headphone Jack", "HP_OUT";
|
||||
mux-int-port = <1>;
|
||||
mux-ext-port = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&audmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_audmux_2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_2>;
|
||||
status = "okay";
|
||||
|
||||
codec: sgtl5000@0a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
clocks = <&clks 201>;
|
||||
VDDA-supply = <®_2p5v>;
|
||||
VDDIO-supply = <®_3p3v>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
hog {
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
||||
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
|
||||
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
|
||||
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
|
||||
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
|
||||
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
|
||||
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
|
||||
MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet_1>;
|
||||
phy-mode = "rgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssi1 {
|
||||
fsl,mode = "i2s-slave";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3_2>;
|
||||
fsl,uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbh1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc1_2>;
|
||||
cd-gpios = <&gpio1 2 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc3_2>;
|
||||
cd-gpios = <&gpio3 9 0>;
|
||||
status = "okay";
|
||||
};
|
|
@ -14,11 +14,6 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
gpio0 = &gpio1;
|
||||
gpio1 = &gpio2;
|
||||
gpio2 = &gpio3;
|
||||
|
@ -26,6 +21,18 @@
|
|||
gpio4 = &gpio5;
|
||||
gpio5 = &gpio6;
|
||||
gpio6 = &gpio7;
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
spi3 = &ecspi4;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@00a01000 {
|
||||
|
@ -81,15 +88,14 @@
|
|||
#size-cells = <1>;
|
||||
reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
|
||||
reg-names = "gpmi-nand", "bch";
|
||||
interrupts = <0 13 0x04>, <0 15 0x04>;
|
||||
interrupt-names = "gpmi-dma", "bch";
|
||||
interrupts = <0 15 0x04>;
|
||||
interrupt-names = "bch";
|
||||
clocks = <&clks 152>, <&clks 153>, <&clks 151>,
|
||||
<&clks 150>, <&clks 149>;
|
||||
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
|
||||
"gpmi_bch_apb", "per1_bch";
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
fsl,gpmi-dma-channel = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -184,6 +190,8 @@
|
|||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -197,6 +205,9 @@
|
|||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
clocks = <&clks 178>;
|
||||
dmas = <&sdma 37 1 0>,
|
||||
<&sdma 38 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <38 37>;
|
||||
status = "disabled";
|
||||
|
@ -207,6 +218,9 @@
|
|||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
clocks = <&clks 179>;
|
||||
dmas = <&sdma 41 1 0>,
|
||||
<&sdma 42 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <42 41>;
|
||||
status = "disabled";
|
||||
|
@ -217,6 +231,9 @@
|
|||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
clocks = <&clks 180>;
|
||||
dmas = <&sdma 45 1 0>,
|
||||
<&sdma 46 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <46 45>;
|
||||
status = "disabled";
|
||||
|
@ -278,17 +295,23 @@
|
|||
};
|
||||
|
||||
can1: flexcan@02090000 {
|
||||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02090000 0x4000>;
|
||||
interrupts = <0 110 0x04>;
|
||||
clocks = <&clks 108>, <&clks 109>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
can2: flexcan@02094000 {
|
||||
compatible = "fsl,imx6q-flexcan";
|
||||
reg = <0x02094000 0x4000>;
|
||||
interrupts = <0 111 0x04>;
|
||||
clocks = <&clks 110>, <&clks 111>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
gpt: gpt@02098000 {
|
||||
compatible = "fsl,imx6q-gpt";
|
||||
compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
|
||||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <0 55 0x04>;
|
||||
clocks = <&clks 119>, <&clks 120>;
|
||||
|
@ -491,6 +514,13 @@
|
|||
};
|
||||
};
|
||||
|
||||
tempmon: tempmon {
|
||||
compatible = "fsl,imx6q-tempmon";
|
||||
interrupts = <0 49 0x04>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
fsl,tempmon-data = <&ocotp>;
|
||||
};
|
||||
|
||||
usbphy1: usbphy@020c9000 {
|
||||
compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
|
||||
reg = <0x020c9000 0x1000>;
|
||||
|
@ -546,6 +576,713 @@
|
|||
reg = <0x020e0000 0x38>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
|
||||
audmux {
|
||||
pinctrl_audmux_1: audmux-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
|
||||
MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
|
||||
MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
|
||||
MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux_2: audmux-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_audmux_3: audmux-3 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
|
||||
MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
|
||||
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi1 {
|
||||
pinctrl_ecspi1_1: ecspi1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1_2: ecspi1grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
||||
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
||||
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ecspi3 {
|
||||
pinctrl_ecspi3_1: ecspi3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
|
||||
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
enet {
|
||||
pinctrl_enet_1: enetgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_2: enetgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet_3: enetgrp-3 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
||||
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
esai {
|
||||
pinctrl_esai_1: esaigrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
|
||||
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
|
||||
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
|
||||
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
|
||||
MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
|
||||
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
|
||||
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
|
||||
MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
|
||||
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_esai_2: esaigrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
|
||||
MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
|
||||
MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
|
||||
MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
|
||||
MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
|
||||
MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
|
||||
MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
|
||||
MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
|
||||
MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
|
||||
MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
flexcan1 {
|
||||
pinctrl_flexcan1_1: flexcan1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
|
||||
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1_2: flexcan1grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
|
||||
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
flexcan2 {
|
||||
pinctrl_flexcan2_1: flexcan2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
|
||||
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
gpmi-nand {
|
||||
pinctrl_gpmi_nand_1: gpmi-nand-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
|
||||
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
|
||||
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
|
||||
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
|
||||
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
|
||||
MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_hdcp {
|
||||
pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_cec {
|
||||
pinctrl_hdmi_cec_1: hdmicecgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hdmi_cec_2: hdmicecgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1 {
|
||||
pinctrl_i2c1_1: i2c1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_2: i2c1grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
||||
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c2 {
|
||||
pinctrl_i2c2_1: i2c2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_2: i2c2grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_3: i2c2grp-3 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c3 {
|
||||
pinctrl_i2c3_1: i2c3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_2: i2c3grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_3: i2c3grp-3 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3_4: i2c3grp-4 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
||||
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ipu1 {
|
||||
pinctrl_ipu1_1: ipu1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
||||
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
||||
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
||||
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
||||
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
|
||||
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
||||
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
||||
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
||||
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
||||
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
||||
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
||||
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
||||
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
||||
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
||||
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
||||
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
||||
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
||||
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
||||
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
||||
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
||||
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
||||
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
||||
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
||||
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
||||
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
||||
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
||||
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
||||
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
||||
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
|
||||
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
|
||||
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
|
||||
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
|
||||
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
|
||||
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
|
||||
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
|
||||
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
|
||||
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
mlb {
|
||||
pinctrl_mlb_1: mlbgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
|
||||
MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
|
||||
MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mlb_2: mlbgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
|
||||
MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
|
||||
MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pinctrl_pwm0_1: pwm0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pinctrl_pwm3_1: pwm3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif {
|
||||
pinctrl_spdif_1: spdifgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif_2: spdifgrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
|
||||
MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
pinctrl_uart1_1: uart1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
pinctrl_uart2_1: uart2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart3 {
|
||||
pinctrl_uart3_1: uart3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3_2: uart3grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
|
||||
MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4 {
|
||||
pinctrl_uart4_1: uart4grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
|
||||
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg {
|
||||
pinctrl_usbotg_1: usbotggrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg_2: usbotggrp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbh2 {
|
||||
pinctrl_usbh2_1: usbh2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
|
||||
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh2_2: usbh2grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usbh3 {
|
||||
pinctrl_usbh3_1: usbh3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
|
||||
MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbh3_2: usbh3grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc1 {
|
||||
pinctrl_usdhc1_1: usdhc1grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
|
||||
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
|
||||
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
|
||||
MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_2: usdhc1grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
|
||||
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
|
||||
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
|
||||
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
|
||||
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
|
||||
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc2 {
|
||||
pinctrl_usdhc2_1: usdhc2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
||||
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
||||
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
||||
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_2: usdhc2grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
||||
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
||||
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
||||
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
||||
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
||||
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc3 {
|
||||
pinctrl_usdhc3_1: usdhc3grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
||||
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
||||
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
||||
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_2: usdhc3grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
||||
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
||||
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
||||
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
||||
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
||||
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
usdhc4 {
|
||||
pinctrl_usdhc4_1: usdhc4grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
||||
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
||||
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
||||
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc4_2: usdhc4grp-2 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
||||
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
||||
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
||||
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
||||
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
||||
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
weim {
|
||||
pinctrl_weim_cs0_1: weim_cs0grp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_weim_nor_1: weim_norgrp-1 {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
|
||||
MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
|
||||
MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
|
||||
/* data */
|
||||
MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
|
||||
MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
|
||||
/* address */
|
||||
MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
|
||||
MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
|
||||
MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
|
||||
MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
|
||||
MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
|
||||
MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
|
||||
MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
|
||||
MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
|
||||
MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ldb: ldb@020e0008 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
@ -555,13 +1292,11 @@
|
|||
|
||||
lvds-channel@0 {
|
||||
reg = <0>;
|
||||
crtcs = <&ipu1 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lvds-channel@1 {
|
||||
reg = <1>;
|
||||
crtcs = <&ipu1 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
@ -582,6 +1317,7 @@
|
|||
interrupts = <0 2 0x04>;
|
||||
clocks = <&clks 155>, <&clks 155>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
||||
};
|
||||
};
|
||||
|
@ -751,8 +1487,8 @@
|
|||
clocks = <&clks 196>;
|
||||
};
|
||||
|
||||
ocotp@021bc000 {
|
||||
compatible = "fsl,imx6q-ocotp";
|
||||
ocotp: ocotp@021bc000 {
|
||||
compatible = "fsl,imx6q-ocotp", "syscon";
|
||||
reg = <0x021bc000 0x4000>;
|
||||
};
|
||||
|
||||
|
@ -791,6 +1527,8 @@
|
|||
interrupts = <0 27 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -800,6 +1538,8 @@
|
|||
interrupts = <0 28 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -809,6 +1549,8 @@
|
|||
interrupts = <0 29 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -818,6 +1560,8 @@
|
|||
interrupts = <0 30 0x04>;
|
||||
clocks = <&clks 160>, <&clks 161>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -152,32 +152,41 @@
|
|||
};
|
||||
|
||||
uart5: serial@02018000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <0 30 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <0 26 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@02024000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02024000 0x4000>;
|
||||
interrupts = <0 27 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -186,6 +195,9 @@
|
|||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <0 46 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI1>;
|
||||
dmas = <&sdma 37 1 0>,
|
||||
<&sdma 38 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -195,6 +207,9 @@
|
|||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <0 47 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI2>;
|
||||
dmas = <&sdma 41 1 0>,
|
||||
<&sdma 42 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -204,27 +219,36 @@
|
|||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <0 48 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_SSI3>;
|
||||
dmas = <&sdma 45 1 0>,
|
||||
<&sdma 46 1 0>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@02034000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <0 28 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@02038000 {
|
||||
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
|
||||
compatible = "fsl,imx6sl-uart",
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02038000 0x4000>;
|
||||
interrupts = <0 29 0x04>;
|
||||
clocks = <&clks IMX6SL_CLK_UART>,
|
||||
<&clks IMX6SL_CLK_UART_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
@ -594,6 +618,7 @@
|
|||
clocks = <&clks IMX6SL_CLK_SDMA>,
|
||||
<&clks IMX6SL_CLK_SDMA>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
|
||||
};
|
||||
|
||||
|
|
|
@ -50,6 +50,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c0_1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_1>;
|
||||
|
|
|
@ -119,7 +119,7 @@ enum imx5_clks {
|
|||
srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
|
||||
spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
|
||||
spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
|
||||
clk_max
|
||||
ocram, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
|
@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
|
||||
clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
|
||||
clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
|
||||
clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
|
||||
clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
|
||||
clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
|
||||
clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
|
||||
|
|
|
@ -288,6 +288,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
struct device_node *np;
|
||||
void __iomem *base;
|
||||
int i, irq;
|
||||
int ret;
|
||||
|
||||
clk[dummy] = imx_clk_fixed("dummy", 0);
|
||||
clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
|
||||
|
@ -592,6 +593,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk_prepare_enable(clk[usbphy2_gate]);
|
||||
}
|
||||
|
||||
/*
|
||||
* Let's initially set up CLKO with OSC24M, since this configuration
|
||||
* is widely used by imx6q board designs to clock audio codec.
|
||||
*/
|
||||
ret = clk_set_parent(clk[cko2_sel], clk[osc]);
|
||||
if (!ret)
|
||||
ret = clk_set_parent(clk[cko], clk[cko2]);
|
||||
if (ret)
|
||||
pr_warn("failed to set up CLKO: %d\n", ret);
|
||||
|
||||
/* Set initial power mode */
|
||||
imx6q_set_lpm(WAIT_CLOCKED);
|
||||
|
||||
|
|
|
@ -162,30 +162,6 @@ static int ar8031_phy_fixup(struct phy_device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void __init imx6q_sabrelite_cko1_setup(void)
|
||||
{
|
||||
struct clk *cko1_sel, *ahb, *cko1;
|
||||
unsigned long rate;
|
||||
|
||||
cko1_sel = clk_get_sys(NULL, "cko1_sel");
|
||||
ahb = clk_get_sys(NULL, "ahb");
|
||||
cko1 = clk_get_sys(NULL, "cko1");
|
||||
if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
|
||||
pr_err("cko1 setup failed!\n");
|
||||
goto put_clk;
|
||||
}
|
||||
clk_set_parent(cko1_sel, ahb);
|
||||
rate = clk_round_rate(cko1, 16000000);
|
||||
clk_set_rate(cko1, rate);
|
||||
put_clk:
|
||||
if (!IS_ERR(cko1_sel))
|
||||
clk_put(cko1_sel);
|
||||
if (!IS_ERR(ahb))
|
||||
clk_put(ahb);
|
||||
if (!IS_ERR(cko1))
|
||||
clk_put(cko1);
|
||||
}
|
||||
|
||||
#define PHY_ID_AR8031 0x004dd074
|
||||
|
||||
static void __init imx6q_enet_phy_init(void)
|
||||
|
@ -200,45 +176,6 @@ static void __init imx6q_enet_phy_init(void)
|
|||
}
|
||||
}
|
||||
|
||||
static void __init imx6q_sabresd_cko1_setup(void)
|
||||
{
|
||||
struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
|
||||
unsigned long rate;
|
||||
|
||||
cko1_sel = clk_get_sys(NULL, "cko1_sel");
|
||||
pll4 = clk_get_sys(NULL, "pll4_audio");
|
||||
pll4_post = clk_get_sys(NULL, "pll4_post_div");
|
||||
cko1 = clk_get_sys(NULL, "cko1");
|
||||
if (IS_ERR(cko1_sel) || IS_ERR(pll4)
|
||||
|| IS_ERR(pll4_post) || IS_ERR(cko1)) {
|
||||
pr_err("cko1 setup failed!\n");
|
||||
goto put_clk;
|
||||
}
|
||||
/*
|
||||
* Setting pll4 at 768MHz (24MHz * 32)
|
||||
* So its child clock can get 24MHz easily
|
||||
*/
|
||||
clk_set_rate(pll4, 768000000);
|
||||
|
||||
clk_set_parent(cko1_sel, pll4_post);
|
||||
rate = clk_round_rate(cko1, 24000000);
|
||||
clk_set_rate(cko1, rate);
|
||||
put_clk:
|
||||
if (!IS_ERR(cko1_sel))
|
||||
clk_put(cko1_sel);
|
||||
if (!IS_ERR(pll4_post))
|
||||
clk_put(pll4_post);
|
||||
if (!IS_ERR(pll4))
|
||||
clk_put(pll4);
|
||||
if (!IS_ERR(cko1))
|
||||
clk_put(cko1);
|
||||
}
|
||||
|
||||
static void __init imx6q_sabresd_init(void)
|
||||
{
|
||||
imx6q_sabresd_cko1_setup();
|
||||
}
|
||||
|
||||
static void __init imx6q_1588_init(void)
|
||||
{
|
||||
struct regmap *gpr;
|
||||
|
@ -255,12 +192,6 @@ static void __init imx6q_1588_init(void)
|
|||
|
||||
static void __init imx6q_init_machine(void)
|
||||
{
|
||||
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
|
||||
imx6q_sabrelite_cko1_setup();
|
||||
else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
|
||||
of_machine_is_compatible("fsl,imx6dl-sabresd"))
|
||||
imx6q_sabresd_init();
|
||||
|
||||
imx6q_enet_phy_init();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
|
Loading…
Reference in a new issue