Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Daniel writes: "- some register magic to fix hsw crw (Paulo&Ben) - fix backlight destruction for cpu edp (Jani) - fix gen ch7xxx dvo ->get_hw_state - fixup the plane->pipe fixup code, the broken version massively angers the modeset sanity checks - kill pipe A quirk for i855gm, otherwise I get a black screen with the above patch - fixup for gem_get_page helper (Chris) - fixup guardband clipping w/a (Ken), without this mesa master can erronously drop vertices on snb, mesa 9.0 has the optimization reverted - another pageflip vs. modeset fix - kill bogus BUG_ON which broke ums+gem from Willy Tarreau (gasp, people are still using this!)" * 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: fix non-DP-D eDP backlight cleanup and module reload drm/i915: HSW CRW stability magic drm/i915/dvo-ch7xxx: fix get_hw_state drm/i915: fixup the plane->pipe fixup code drm/i915: rip out the pipe A quirk for i855gm drm/i915: disable wc gtt pte mappings on gen2 drm/i915: fixup i915_gem_object_get_page inline helper drm/i915: Disallow preallocation of requests drm/i915: Set guardband clipping workaround bit in the right register. drm/i915: paper over a pipe-enable vs pageflip race drm/i915: remove useless BUG_ON which caused a regression in 3.5.
This commit is contained in:
Dave Airlie
commit
3459f62047
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@ -667,7 +667,7 @@ static int intel_gtt_init(void)
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gtt_map_size = intel_private.base.gtt_total_entries * 4;
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intel_private.gtt = NULL;
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if (INTEL_GTT_GEN < 6)
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if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2)
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intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr,
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gtt_map_size);
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if (intel_private.gtt == NULL)
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@ -303,10 +303,10 @@ static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo)
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ch7xxx_readb(dvo, CH7xxx_PM, &val);
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if (val & CH7xxx_PM_FPD)
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return false;
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else
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if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP))
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return true;
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else
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return false;
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}
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static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
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@ -1341,9 +1341,14 @@ int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
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static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
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{
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struct scatterlist *sg = obj->pages->sgl;
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while (n >= SG_MAX_SINGLE_ALLOC) {
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int nents = obj->pages->nents;
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while (nents > SG_MAX_SINGLE_ALLOC) {
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if (n < SG_MAX_SINGLE_ALLOC - 1)
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break;
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sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
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n -= SG_MAX_SINGLE_ALLOC - 1;
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nents -= SG_MAX_SINGLE_ALLOC - 1;
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}
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return sg_page(sg+n);
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}
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@ -1427,7 +1432,7 @@ int __must_check i915_gpu_idle(struct drm_device *dev);
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int __must_check i915_gem_idle(struct drm_device *dev);
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int i915_add_request(struct intel_ring_buffer *ring,
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struct drm_file *file,
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struct drm_i915_gem_request *request);
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u32 *seqno);
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int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
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uint32_t seqno);
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int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
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@ -1955,11 +1955,12 @@ i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
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int
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i915_add_request(struct intel_ring_buffer *ring,
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struct drm_file *file,
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struct drm_i915_gem_request *request)
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u32 *out_seqno)
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{
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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uint32_t seqno;
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struct drm_i915_gem_request *request;
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u32 request_ring_position;
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u32 seqno;
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int was_empty;
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int ret;
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@ -1974,11 +1975,9 @@ i915_add_request(struct intel_ring_buffer *ring,
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if (ret)
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return ret;
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if (request == NULL) {
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request = kmalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL)
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return -ENOMEM;
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}
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request = kmalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL)
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return -ENOMEM;
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seqno = i915_gem_next_request_seqno(ring);
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@ -2030,6 +2029,8 @@ i915_add_request(struct intel_ring_buffer *ring,
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}
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}
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if (out_seqno)
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*out_seqno = seqno;
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return 0;
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}
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@ -3959,6 +3960,9 @@ i915_gem_init_hw(struct drm_device *dev)
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if (!intel_enable_gtt())
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return -EIO;
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if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1))
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I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
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i915_gem_l3_remap(dev);
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i915_gem_init_swizzling(dev);
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@ -4098,7 +4102,6 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
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}
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BUG_ON(!list_empty(&dev_priv->mm.active_list));
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BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
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mutex_unlock(&dev->struct_mutex);
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ret = drm_irq_install(dev);
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@ -521,7 +521,7 @@
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*/
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# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
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#define _3D_CHICKEN3 0x02090
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#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 << 5)
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#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
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#define MI_MODE 0x0209c
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# define VS_TIMER_DISPATCH (1 << 6)
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@ -3253,6 +3253,16 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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if (HAS_PCH_CPT(dev))
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intel_cpt_verify_modeset(dev, intel_crtc->pipe);
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/*
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* There seems to be a race in PCH platform hw (at least on some
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* outputs) where an enabled pipe still completes any pageflip right
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* away (as if the pipe is off) instead of waiting for vblank. As soon
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* as the first vblank happend, everything works as expected. Hence just
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* wait for one vblank before returning to avoid strange things
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* happening.
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*/
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intel_wait_for_vblank(dev, intel_crtc->pipe);
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}
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static void ironlake_crtc_disable(struct drm_crtc *crtc)
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@ -7892,8 +7902,7 @@ static struct intel_quirk intel_quirks[] = {
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/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
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{ 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
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/* 855 & before need to leave pipe A & dpll A up */
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{ 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
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/* 830/845 need to leave pipe A & dpll A up */
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{ 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
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{ 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
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@ -8049,29 +8058,42 @@ static void intel_enable_pipe_a(struct drm_device *dev)
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}
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static bool
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intel_check_plane_mapping(struct intel_crtc *crtc)
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{
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struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
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u32 reg, val;
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if (dev_priv->num_pipe == 1)
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return true;
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reg = DSPCNTR(!crtc->plane);
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val = I915_READ(reg);
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if ((val & DISPLAY_PLANE_ENABLE) &&
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(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
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return false;
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return true;
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}
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static void intel_sanitize_crtc(struct intel_crtc *crtc)
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{
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg, val;
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u32 reg;
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/* Clear any frame start delays used for debugging left by the BIOS */
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reg = PIPECONF(crtc->pipe);
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I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
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/* We need to sanitize the plane -> pipe mapping first because this will
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* disable the crtc (and hence change the state) if it is wrong. */
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if (!HAS_PCH_SPLIT(dev)) {
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* disable the crtc (and hence change the state) if it is wrong. Note
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* that gen4+ has a fixed plane -> pipe mapping. */
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if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
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struct intel_connector *connector;
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bool plane;
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reg = DSPCNTR(crtc->plane);
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val = I915_READ(reg);
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if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
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(!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
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goto ok;
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DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
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crtc->base.base.id);
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@ -8095,7 +8117,6 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
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WARN_ON(crtc->active);
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crtc->base.enabled = false;
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}
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ok:
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if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
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crtc->pipe == PIPE_A && !crtc->active) {
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@ -2369,8 +2369,9 @@ static void
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intel_dp_destroy(struct drm_connector *connector)
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{
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struct drm_device *dev = connector->dev;
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struct intel_dp *intel_dp = intel_attached_dp(connector);
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if (intel_dpd_is_edp(dev))
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if (is_edp(intel_dp))
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intel_panel_destroy_backlight(dev);
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drm_sysfs_connector_remove(connector);
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@ -209,7 +209,6 @@ static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
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}
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static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
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struct drm_i915_gem_request *request,
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void (*tail)(struct intel_overlay *))
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{
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struct drm_device *dev = overlay->dev;
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@ -218,12 +217,10 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
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int ret;
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BUG_ON(overlay->last_flip_req);
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ret = i915_add_request(ring, NULL, request);
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if (ret) {
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kfree(request);
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return ret;
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}
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overlay->last_flip_req = request->seqno;
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ret = i915_add_request(ring, NULL, &overlay->last_flip_req);
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if (ret)
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return ret;
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overlay->flip_tail = tail;
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ret = i915_wait_seqno(ring, overlay->last_flip_req);
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if (ret)
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@ -240,7 +237,6 @@ static int intel_overlay_on(struct intel_overlay *overlay)
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struct drm_device *dev = overlay->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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struct drm_i915_gem_request *request;
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int ret;
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BUG_ON(overlay->active);
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@ -248,17 +244,9 @@ static int intel_overlay_on(struct intel_overlay *overlay)
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WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
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request = kzalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL) {
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ret = -ENOMEM;
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goto out;
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}
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ret = intel_ring_begin(ring, 4);
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if (ret) {
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kfree(request);
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goto out;
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}
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
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intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
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@ -266,9 +254,7 @@ static int intel_overlay_on(struct intel_overlay *overlay)
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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ret = intel_overlay_do_wait_request(overlay, request, NULL);
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out:
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return ret;
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return intel_overlay_do_wait_request(overlay, NULL);
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}
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/* overlay needs to be enabled in OCMD reg */
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@ -278,17 +264,12 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
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struct drm_device *dev = overlay->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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struct drm_i915_gem_request *request;
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u32 flip_addr = overlay->flip_addr;
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u32 tmp;
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int ret;
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BUG_ON(!overlay->active);
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request = kzalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL)
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return -ENOMEM;
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if (load_polyphase_filter)
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flip_addr |= OFC_UPDATE;
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@ -298,22 +279,14 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
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DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
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ret = intel_ring_begin(ring, 2);
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if (ret) {
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kfree(request);
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if (ret)
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return ret;
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}
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intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
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intel_ring_emit(ring, flip_addr);
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intel_ring_advance(ring);
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ret = i915_add_request(ring, NULL, request);
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if (ret) {
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kfree(request);
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return ret;
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}
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overlay->last_flip_req = request->seqno;
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return 0;
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return i915_add_request(ring, NULL, &overlay->last_flip_req);
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}
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static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
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@ -349,15 +322,10 @@ static int intel_overlay_off(struct intel_overlay *overlay)
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
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u32 flip_addr = overlay->flip_addr;
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struct drm_i915_gem_request *request;
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int ret;
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BUG_ON(!overlay->active);
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request = kzalloc(sizeof(*request), GFP_KERNEL);
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if (request == NULL)
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return -ENOMEM;
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/* According to intel docs the overlay hw may hang (when switching
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* off) without loading the filter coeffs. It is however unclear whether
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* this applies to the disabling of the overlay or to the switching off
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@ -365,10 +333,9 @@ static int intel_overlay_off(struct intel_overlay *overlay)
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flip_addr |= OFC_UPDATE;
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ret = intel_ring_begin(ring, 6);
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if (ret) {
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kfree(request);
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if (ret)
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return ret;
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}
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/* wait for overlay to go idle */
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intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
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intel_ring_emit(ring, flip_addr);
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@ -379,8 +346,7 @@ static int intel_overlay_off(struct intel_overlay *overlay)
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intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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intel_ring_advance(ring);
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||||
return intel_overlay_do_wait_request(overlay, request,
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intel_overlay_off_tail);
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||||
return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail);
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||||
}
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||||
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||||
/* recover from an interruption due to a signal
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||||
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|
@ -425,24 +391,16 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
|
|||
return 0;
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||||
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||||
if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
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||||
struct drm_i915_gem_request *request;
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||||
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||||
/* synchronous slowpath */
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||||
request = kzalloc(sizeof(*request), GFP_KERNEL);
|
||||
if (request == NULL)
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||||
return -ENOMEM;
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||||
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||||
ret = intel_ring_begin(ring, 2);
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||||
if (ret) {
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||||
kfree(request);
|
||||
if (ret)
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||||
return ret;
|
||||
}
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||||
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||||
intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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||||
intel_ring_emit(ring, MI_NOOP);
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||||
intel_ring_advance(ring);
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||||
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||||
ret = intel_overlay_do_wait_request(overlay, request,
|
||||
ret = intel_overlay_do_wait_request(overlay,
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||||
intel_overlay_release_old_vid_tail);
|
||||
if (ret)
|
||||
return ret;
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||||
|
|
|
|||
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|
@ -3442,8 +3442,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
|
|||
GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
|
||||
|
||||
/* Bspec says we need to always set all mask bits. */
|
||||
I915_WRITE(_3D_CHICKEN, (0xFFFF << 16) |
|
||||
_3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL);
|
||||
I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
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||||
_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
|
||||
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||||
/*
|
||||
* According to the spec the following bits should be
|
||||
|
|
|
|||
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