drm/i915: Add second slice l3 remapping
Certain HSW SKUs have a second bank of L3. This L3 remapping has a separate register set, and interrupt from the first "slice". A slice is simply a term to define some subset of the GPU's l3 cache. This patch implements both the interrupt handler, and ability to communicate with userspace about this second slice. v2: Remove redundant check about non-existent slice. Change warning about interrupts of unknown slices to WARN_ON_ONCE Handle the case where we get 2 slice interrupts concurrently, and switch the tracking of interrupts to be non-destructive (all Ville) Don't enable/mask the second slice parity interrupt for ivb/vlv (even though all docs I can find claim it's rsvd) (Ville + Bryan) Keep BYT excluded from L3 parity v3: Fix the slice = ffs to be decremented by one (found by Ville). When I initially did my testing on the series, I was using 1-based slice counting, so this code was correct. Not sure why my simpler tests that I've been running since then didn't pick it up sooner. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ben Widawsky
Daniel Vetter
parent
1c966dd26b
commit
35a85ac606
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@ -917,9 +917,11 @@ struct i915_ums_state {
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int mm_suspended;
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};
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#define MAX_L3_SLICES 2
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struct intel_l3_parity {
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u32 *remap_info;
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u32 *remap_info[MAX_L3_SLICES];
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struct work_struct error_work;
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int which_slice;
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};
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struct i915_gem_mm {
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@ -1686,6 +1688,7 @@ struct drm_i915_file_private {
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#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
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#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
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#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_GPU_CACHE(dev))
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#define GT_FREQUENCY_MULTIPLIER 50
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@ -1946,7 +1949,7 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
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int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
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int __must_check i915_gem_init(struct drm_device *dev);
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int __must_check i915_gem_init_hw(struct drm_device *dev);
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void i915_gem_l3_remap(struct drm_device *dev);
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void i915_gem_l3_remap(struct drm_device *dev, int slice);
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void i915_gem_init_swizzling(struct drm_device *dev);
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void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
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int __must_check i915_gpu_idle(struct drm_device *dev);
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@ -4222,16 +4222,15 @@ i915_gem_idle(struct drm_device *dev)
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return 0;
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}
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void i915_gem_l3_remap(struct drm_device *dev)
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void i915_gem_l3_remap(struct drm_device *dev, int slice)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
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u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
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u32 misccpctl;
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int i;
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if (!HAS_L3_GPU_CACHE(dev))
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return;
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if (!dev_priv->l3_parity.remap_info)
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if (!HAS_L3_GPU_CACHE(dev) || !remap_info)
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return;
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misccpctl = I915_READ(GEN7_MISCCPCTL);
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@ -4239,17 +4238,17 @@ void i915_gem_l3_remap(struct drm_device *dev)
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POSTING_READ(GEN7_MISCCPCTL);
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for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
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u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
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if (remap && remap != dev_priv->l3_parity.remap_info[i/4])
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u32 remap = I915_READ(reg_base + i);
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if (remap && remap != remap_info[i/4])
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DRM_DEBUG("0x%x was already programmed to %x\n",
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GEN7_L3LOG_BASE + i, remap);
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if (remap && !dev_priv->l3_parity.remap_info[i/4])
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reg_base + i, remap);
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if (remap && !remap_info[i/4])
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DRM_DEBUG_DRIVER("Clearing remapped register\n");
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I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]);
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I915_WRITE(reg_base + i, remap_info[i/4]);
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}
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/* Make sure all the writes land before disabling dop clock gating */
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POSTING_READ(GEN7_L3LOG_BASE);
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POSTING_READ(reg_base);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl);
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}
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@ -4343,7 +4342,7 @@ int
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i915_gem_init_hw(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int ret;
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int ret, i;
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if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
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return -EIO;
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@ -4362,7 +4361,8 @@ i915_gem_init_hw(struct drm_device *dev)
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I915_WRITE(GEN7_MSG_CTL, temp);
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}
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i915_gem_l3_remap(dev);
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for (i = 0; i < NUM_L3_SLICES(dev); i++)
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i915_gem_l3_remap(dev, i);
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i915_gem_init_swizzling(dev);
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@ -888,9 +888,10 @@ static void ivybridge_parity_work(struct work_struct *work)
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drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
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l3_parity.error_work);
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u32 error_status, row, bank, subbank;
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char *parity_event[5];
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char *parity_event[6];
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uint32_t misccpctl;
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unsigned long flags;
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uint8_t slice = 0;
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/* We must turn off DOP level clock gating to access the L3 registers.
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* In order to prevent a get/put style interface, acquire struct mutex
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@ -898,45 +899,64 @@ static void ivybridge_parity_work(struct work_struct *work)
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*/
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mutex_lock(&dev_priv->dev->struct_mutex);
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/* If we've screwed up tracking, just let the interrupt fire again */
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if (WARN_ON(!dev_priv->l3_parity.which_slice))
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goto out;
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misccpctl = I915_READ(GEN7_MISCCPCTL);
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I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
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POSTING_READ(GEN7_MISCCPCTL);
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error_status = I915_READ(GEN7_L3CDERRST1);
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row = GEN7_PARITY_ERROR_ROW(error_status);
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bank = GEN7_PARITY_ERROR_BANK(error_status);
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subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
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while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
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u32 reg;
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I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
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GEN7_L3CDERRST1_ENABLE);
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POSTING_READ(GEN7_L3CDERRST1);
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slice--;
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if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
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break;
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dev_priv->l3_parity.which_slice &= ~(1<<slice);
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reg = GEN7_L3CDERRST1 + (slice * 0x200);
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error_status = I915_READ(reg);
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row = GEN7_PARITY_ERROR_ROW(error_status);
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bank = GEN7_PARITY_ERROR_BANK(error_status);
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subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
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I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
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POSTING_READ(reg);
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parity_event[0] = I915_L3_PARITY_UEVENT "=1";
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parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
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parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
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parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
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parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
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parity_event[5] = NULL;
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kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
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KOBJ_CHANGE, parity_event);
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DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
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slice, row, bank, subbank);
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kfree(parity_event[4]);
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kfree(parity_event[3]);
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kfree(parity_event[2]);
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kfree(parity_event[1]);
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}
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I915_WRITE(GEN7_MISCCPCTL, misccpctl);
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out:
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WARN_ON(dev_priv->l3_parity.which_slice);
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spin_lock_irqsave(&dev_priv->irq_lock, flags);
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ilk_enable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
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ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
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spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
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mutex_unlock(&dev_priv->dev->struct_mutex);
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parity_event[0] = I915_L3_PARITY_UEVENT "=1";
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parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
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parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
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parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
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parity_event[4] = NULL;
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kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
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KOBJ_CHANGE, parity_event);
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DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
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row, bank, subbank);
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kfree(parity_event[3]);
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kfree(parity_event[2]);
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kfree(parity_event[1]);
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}
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static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
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static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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@ -944,9 +964,16 @@ static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
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return;
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spin_lock(&dev_priv->irq_lock);
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ilk_disable_gt_irq(dev_priv, GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
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ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
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spin_unlock(&dev_priv->irq_lock);
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iir &= GT_PARITY_ERROR(dev);
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if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
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dev_priv->l3_parity.which_slice |= 1 << 1;
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if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
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dev_priv->l3_parity.which_slice |= 1 << 0;
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queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
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}
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@ -981,8 +1008,8 @@ static void snb_gt_irq_handler(struct drm_device *dev,
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i915_handle_error(dev, false);
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}
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if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
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ivybridge_parity_error_irq_handler(dev);
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if (gt_iir & GT_PARITY_ERROR(dev))
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ivybridge_parity_error_irq_handler(dev, gt_iir);
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}
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#define HPD_STORM_DETECT_PERIOD 1000
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@ -2221,8 +2248,8 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
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dev_priv->gt_irq_mask = ~0;
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if (HAS_L3_GPU_CACHE(dev)) {
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/* L3 parity interrupt is always unmasked. */
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dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
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gt_irqs |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
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dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
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gt_irqs |= GT_PARITY_ERROR(dev);
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}
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gt_irqs |= GT_RENDER_USER_INTERRUPT;
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@ -927,6 +927,7 @@
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#define GT_BLT_USER_INTERRUPT (1 << 22)
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#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
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#define GT_BSD_USER_INTERRUPT (1 << 12)
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#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
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#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
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#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
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#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
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@ -937,6 +938,10 @@
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#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
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#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
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#define GT_PARITY_ERROR(dev) \
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(GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
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IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0)
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/* These are all the "old" interrupts */
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#define ILK_BSD_USER_INTERRUPT (1<<5)
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#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
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@ -4747,6 +4752,7 @@
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/* IVYBRIDGE DPF */
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#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
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#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
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#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
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#define GEN7_PARITY_ERROR_VALID (1<<13)
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#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
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@ -4760,6 +4766,7 @@
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#define GEN7_L3CDERRST1_ENABLE (1<<7)
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#define GEN7_L3LOG_BASE 0xB070
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#define HSW_L3LOG_BASE_SLICE1 0xB270
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#define GEN7_L3LOG_SIZE 0x80
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#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
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@ -119,6 +119,7 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
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struct drm_device *drm_dev = dminor->dev;
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struct drm_i915_private *dev_priv = drm_dev->dev_private;
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uint32_t misccpctl;
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int slice = (int)(uintptr_t)attr->private;
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int i, ret;
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count = round_down(count, 4);
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@ -134,9 +135,9 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
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return ret;
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if (IS_HASWELL(drm_dev)) {
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if (dev_priv->l3_parity.remap_info)
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if (dev_priv->l3_parity.remap_info[slice])
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memcpy(buf,
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dev_priv->l3_parity.remap_info + (offset/4),
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dev_priv->l3_parity.remap_info[slice] + (offset/4),
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count);
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else
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memset(buf, 0, count);
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@ -168,6 +169,7 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
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struct drm_device *drm_dev = dminor->dev;
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struct drm_i915_private *dev_priv = drm_dev->dev_private;
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u32 *temp = NULL; /* Just here to make handling failures easy */
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int slice = (int)(uintptr_t)attr->private;
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int ret;
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ret = l3_access_valid(drm_dev, offset);
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@ -178,7 +180,7 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
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if (ret)
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return ret;
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if (!dev_priv->l3_parity.remap_info) {
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if (!dev_priv->l3_parity.remap_info[slice]) {
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temp = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
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if (!temp) {
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mutex_unlock(&drm_dev->struct_mutex);
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@ -198,11 +200,11 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
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* at this point it is left as a TODO.
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*/
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if (temp)
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dev_priv->l3_parity.remap_info = temp;
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dev_priv->l3_parity.remap_info[slice] = temp;
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memcpy(dev_priv->l3_parity.remap_info + (offset/4), buf, count);
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memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);
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i915_gem_l3_remap(drm_dev);
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i915_gem_l3_remap(drm_dev, slice);
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mutex_unlock(&drm_dev->struct_mutex);
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@ -214,7 +216,17 @@ static struct bin_attribute dpf_attrs = {
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL
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.mmap = NULL,
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.private = (void *)0
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};
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static struct bin_attribute dpf_attrs_1 = {
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.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
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.size = GEN7_L3LOG_SIZE,
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.read = i915_l3_read,
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.write = i915_l3_write,
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.mmap = NULL,
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.private = (void *)1
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};
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static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
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@ -525,6 +537,13 @@ void i915_setup_sysfs(struct drm_device *dev)
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ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs);
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if (ret)
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DRM_ERROR("l3 parity sysfs setup failed\n");
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if (NUM_L3_SLICES(dev) > 1) {
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ret = device_create_bin_file(&dev->primary->kdev,
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&dpf_attrs_1);
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if (ret)
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DRM_ERROR("l3 parity slice 1 setup failed\n");
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}
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}
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|
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ret = 0;
|
||||
|
|
@ -548,6 +567,7 @@ void i915_teardown_sysfs(struct drm_device *dev)
|
|||
sysfs_remove_files(&dev->primary->kdev.kobj, vlv_attrs);
|
||||
else
|
||||
sysfs_remove_files(&dev->primary->kdev.kobj, gen6_attrs);
|
||||
device_remove_bin_file(&dev->primary->kdev, &dpf_attrs_1);
|
||||
device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
|
||||
#ifdef CONFIG_PM
|
||||
sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
|
||||
|
|
|
|||
|
|
@ -570,7 +570,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
|
|||
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
|
||||
|
||||
if (HAS_L3_GPU_CACHE(dev))
|
||||
I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
|
||||
I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1000,7 +1000,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
|
|||
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
|
||||
I915_WRITE_IMR(ring,
|
||||
~(ring->irq_enable_mask |
|
||||
GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
|
||||
GT_PARITY_ERROR(dev)));
|
||||
else
|
||||
I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
|
||||
ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
|
||||
|
|
@ -1020,8 +1020,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
|
|||
spin_lock_irqsave(&dev_priv->irq_lock, flags);
|
||||
if (--ring->irq_refcount == 0) {
|
||||
if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
|
||||
I915_WRITE_IMR(ring,
|
||||
~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
|
||||
I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
|
||||
else
|
||||
I915_WRITE_IMR(ring, ~0);
|
||||
ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
|
||||
|
|
|
|||
|
|
@ -38,10 +38,10 @@
|
|||
*
|
||||
* I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
|
||||
* event from the gpu l3 cache. Additional information supplied is ROW,
|
||||
* BANK, SUBBANK of the affected cacheline. Userspace should keep track of
|
||||
* these events and if a specific cache-line seems to have a persistent
|
||||
* error remap it with the l3 remapping tool supplied in intel-gpu-tools.
|
||||
* The value supplied with the event is always 1.
|
||||
* BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
|
||||
* track of these events and if a specific cache-line seems to have a
|
||||
* persistent error remap it with the l3 remapping tool supplied in
|
||||
* intel-gpu-tools. The value supplied with the event is always 1.
|
||||
*
|
||||
* I915_ERROR_UEVENT - Generated upon error detection, currently only via
|
||||
* hangcheck. The error detection event is a good indicator of when things
|
||||
|
|
|
|||
Loading…
Reference in a new issue