drm/i915/cnl: Inherit RPS stuff from previous platforms.
Apparently no change on RPS stuff from previous platforms. v2: Merging to rps related patches in one and also adding missed cases. Cc: David Weinehall <david.weinehall@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: David Weinehall <david.weinehall@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1499373673-25066-1-git-send-email-rodrigo.vivi@intel.com
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@ -1159,7 +1159,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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reqf = I915_READ(GEN6_RPNSWREQ);
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if (IS_GEN9(dev_priv))
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if (INTEL_GEN(dev_priv) >= 9)
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reqf >>= 23;
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else {
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reqf &= ~GEN6_TURBO_DISABLE;
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@ -1181,7 +1181,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
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rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
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rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
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if (IS_GEN9(dev_priv))
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if (INTEL_GEN(dev_priv) >= 9)
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cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
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@ -1210,7 +1210,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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dev_priv->rps.pm_intrmsk_mbz);
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seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
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seq_printf(m, "Render p-state ratio: %d\n",
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(gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
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(gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
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seq_printf(m, "Render p-state VID: %d\n",
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gt_perf_status & 0xff);
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seq_printf(m, "Render p-state limit: %d\n",
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@ -1241,18 +1241,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
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rp_state_cap >> 16) & 0xff;
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max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
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max_freq *= (IS_GEN9_BC(dev_priv) ||
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IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
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intel_gpu_freq(dev_priv, max_freq));
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max_freq = (rp_state_cap & 0xff00) >> 8;
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max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
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max_freq *= (IS_GEN9_BC(dev_priv) ||
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IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
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intel_gpu_freq(dev_priv, max_freq));
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max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
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rp_state_cap >> 0) & 0xff;
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max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
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max_freq *= (IS_GEN9_BC(dev_priv) ||
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IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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intel_gpu_freq(dev_priv, max_freq));
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seq_printf(m, "Max overclocked frequency: %dMHz\n",
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@ -1855,7 +1858,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
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if (ret)
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goto out;
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if (IS_GEN9_BC(dev_priv)) {
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if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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/* Convert GT frequency to 50 HZ units */
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min_gpu_freq =
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dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
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@ -1875,7 +1878,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
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&ia_freq);
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seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
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intel_gpu_freq(dev_priv, (gpu_freq *
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(IS_GEN9_BC(dev_priv) ?
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(IS_GEN9_BC(dev_priv) ||
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IS_CANNONLAKE(dev_priv) ?
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GEN9_FREQ_SCALER : 1))),
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((ia_freq >> 0) & 0xff) * 100,
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((ia_freq >> 8) & 0xff) * 100);
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@ -3522,7 +3522,7 @@ enum skl_disp_power_wells {
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#define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
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#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
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#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
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#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
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#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
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(IS_GEN9_LP(dev_priv) ? \
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INTERVAL_0_833_US(us) : \
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INTERVAL_1_33_US(us)) : \
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@ -3531,7 +3531,7 @@ enum skl_disp_power_wells {
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#define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
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#define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
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#define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
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#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
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#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
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(IS_GEN9_LP(dev_priv) ? \
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INTERVAL_0_833_TO_US(interval) : \
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INTERVAL_1_33_TO_US(interval)) : \
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@ -253,7 +253,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
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ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
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} else {
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u32 rpstat = I915_READ(GEN6_RPSTAT1);
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if (IS_GEN9(dev_priv))
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if (INTEL_GEN(dev_priv) >= 9)
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ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
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@ -5852,7 +5852,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
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* the hw runs at the minimal clock before selecting the desired
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* frequency, if the down threshold expires in that window we will not
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* receive a down interrupt. */
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if (IS_GEN9(dev_priv)) {
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if (INTEL_GEN(dev_priv) >= 9) {
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limits = (dev_priv->rps.max_freq_softlimit) << 23;
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if (val <= dev_priv->rps.min_freq_softlimit)
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limits |= (dev_priv->rps.min_freq_softlimit) << 14;
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@ -5994,7 +5994,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
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if (val != dev_priv->rps.cur_freq) {
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gen6_set_rps_thresholds(dev_priv, val);
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if (IS_GEN9(dev_priv))
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if (INTEL_GEN(dev_priv) >= 9)
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I915_WRITE(GEN6_RPNSWREQ,
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GEN9_FREQUENCY(val));
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else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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@ -6353,7 +6353,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
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dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
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IS_GEN9_BC(dev_priv)) {
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IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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u32 ddcc_status = 0;
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if (sandybridge_pcode_read(dev_priv,
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@ -6366,7 +6366,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
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dev_priv->rps.max_freq);
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}
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if (IS_GEN9_BC(dev_priv)) {
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if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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/* Store the frequency values in 16.66 MHZ units, which is
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* the natural hardware unit for SKL
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*/
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@ -6672,7 +6672,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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/* convert DDR frequency from units of 266.6MHz to bandwidth */
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min_ring_freq = mult_frac(min_ring_freq, 8, 3);
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if (IS_GEN9_BC(dev_priv)) {
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if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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/* Convert GT frequency to 50 HZ units */
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min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
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max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
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@ -6690,7 +6690,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
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int diff = max_gpu_freq - gpu_freq;
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unsigned int ia_freq = 0, ring_freq = 0;
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if (IS_GEN9_BC(dev_priv)) {
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if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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/*
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* ring_freq = 2 * GT. ring_freq is in 100MHz units
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* No floor required for ring frequency on SKL.
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@ -7821,7 +7821,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
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} else if (INTEL_GEN(dev_priv) >= 9) {
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gen9_enable_rc6(dev_priv);
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gen9_enable_rps(dev_priv);
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if (IS_GEN9_BC(dev_priv))
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if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
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gen6_update_ring_freq(dev_priv);
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} else if (IS_BROADWELL(dev_priv)) {
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gen8_enable_rps(dev_priv);
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@ -9066,7 +9066,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
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int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
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{
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if (IS_GEN9(dev_priv))
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if (INTEL_GEN(dev_priv) >= 9)
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return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
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GEN9_FREQ_SCALER);
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else if (IS_CHERRYVIEW(dev_priv))
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int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
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{
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if (IS_GEN9(dev_priv))
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if (INTEL_GEN(dev_priv) >= 9)
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return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
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GT_FREQUENCY_MULTIPLIER);
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else if (IS_CHERRYVIEW(dev_priv))
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