ARM: ep93xx: move timer to its own file
This breaks the timer code out of the core file in preparation for refactoring. Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
d770e558e2
commit
361c81f996
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@ -1,7 +1,7 @@
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#
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# Makefile for the linux kernel.
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#
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obj-y := core.o clock.o
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obj-y := core.o clock.o timer-ep93xx.o
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obj-$(CONFIG_EP93XX_DMA) += dma.o
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@ -22,7 +22,6 @@
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/sys_soc.h>
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#include <linux/timex.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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@ -47,7 +46,6 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "soc.h"
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@ -73,113 +71,6 @@ void __init ep93xx_map_io(void)
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iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
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}
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/*************************************************************************
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* Timer handling for EP93xx
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*************************************************************************
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* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
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* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
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* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
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* is free-running, and can't generate interrupts.
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*
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* The 508 kHz timers are ideal for use for the timer interrupt, as the
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* most common values of HZ divide 508 kHz nicely. We pick one of the 16
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* bit timers (timer 1) since we don't need more than 16 bits of reload
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* value as long as HZ >= 8.
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*
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* The higher clock rate of timer 4 makes it a better choice than the
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* other timers for use in gettimeoffset(), while the fact that it can't
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* generate interrupts means we don't have to worry about not being able
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* to use this timer for something else. We also use timer 4 for keeping
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* track of lost jiffies.
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*/
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#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
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#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
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#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
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#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
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#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
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#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
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#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
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#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
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#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
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#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
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#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
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#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
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#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
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#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
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#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
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#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
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#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
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#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
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#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
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#define EP93XX_TIMER123_CLOCK 508469
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#define EP93XX_TIMER4_CLOCK 983040
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#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
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#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ)
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static unsigned int last_jiffy_time;
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static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
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{
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/* Writing any value clears the timer interrupt */
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__raw_writel(1, EP93XX_TIMER1_CLEAR);
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/* Recover lost jiffies */
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while ((signed long)
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(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
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>= TIMER4_TICKS_PER_JIFFY) {
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last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
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timer_tick();
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}
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return IRQ_HANDLED;
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}
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static struct irqaction ep93xx_timer_irq = {
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.name = "ep93xx timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = ep93xx_timer_interrupt,
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};
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static u32 ep93xx_gettimeoffset(void)
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{
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int offset;
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offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
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/*
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* Timer 4 is based on a 983.04 kHz reference clock,
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* so dividing by 983040 gives the fraction of a second,
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* so dividing by 0.983040 converts to uS.
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* Refactor the calculation to avoid overflow.
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* Finally, multiply by 1000 to give nS.
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*/
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return (offset + (53 * offset / 3072)) * 1000;
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}
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void __init ep93xx_timer_init(void)
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{
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u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
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EP93XX_TIMER123_CONTROL_CLKSEL;
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arch_gettimeoffset = ep93xx_gettimeoffset;
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/* Enable periodic HZ timer. */
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__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
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__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
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__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
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EP93XX_TIMER1_CONTROL);
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/* Enable lost jiffy timer. */
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__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
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EP93XX_TIMER4_VALUE_HIGH);
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setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
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}
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/*************************************************************************
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* EP93xx IRQ handling
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*************************************************************************/
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112
arch/arm/mach-ep93xx/timer-ep93xx.c
Normal file
112
arch/arm/mach-ep93xx/timer-ep93xx.c
Normal file
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@ -0,0 +1,112 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/mach/time.h>
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#include "soc.h"
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/*************************************************************************
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* Timer handling for EP93xx
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*************************************************************************
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* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
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* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
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* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
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* is free-running, and can't generate interrupts.
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*
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* The 508 kHz timers are ideal for use for the timer interrupt, as the
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* most common values of HZ divide 508 kHz nicely. We pick one of the 16
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* bit timers (timer 1) since we don't need more than 16 bits of reload
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* value as long as HZ >= 8.
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*
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* The higher clock rate of timer 4 makes it a better choice than the
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* other timers for use in gettimeoffset(), while the fact that it can't
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* generate interrupts means we don't have to worry about not being able
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* to use this timer for something else. We also use timer 4 for keeping
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* track of lost jiffies.
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*/
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#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
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#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
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#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
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#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
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#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
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#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
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#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
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#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
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#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
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#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
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#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
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#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
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#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
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#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
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#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
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#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
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#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
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#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
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#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
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#define EP93XX_TIMER123_CLOCK 508469
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#define EP93XX_TIMER4_CLOCK 983040
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#define TIMER1_RELOAD ((EP93XX_TIMER123_CLOCK / HZ) - 1)
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#define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(EP93XX_TIMER4_CLOCK, HZ)
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static unsigned int last_jiffy_time;
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static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
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{
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/* Writing any value clears the timer interrupt */
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__raw_writel(1, EP93XX_TIMER1_CLEAR);
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/* Recover lost jiffies */
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while ((signed long)
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(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
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>= TIMER4_TICKS_PER_JIFFY) {
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last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
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timer_tick();
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}
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return IRQ_HANDLED;
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}
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static struct irqaction ep93xx_timer_irq = {
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.name = "ep93xx timer",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = ep93xx_timer_interrupt,
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};
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static u32 ep93xx_gettimeoffset(void)
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{
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int offset;
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offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
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/*
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* Timer 4 is based on a 983.04 kHz reference clock,
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* so dividing by 983040 gives the fraction of a second,
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* so dividing by 0.983040 converts to uS.
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* Refactor the calculation to avoid overflow.
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* Finally, multiply by 1000 to give nS.
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*/
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return (offset + (53 * offset / 3072)) * 1000;
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}
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void __init ep93xx_timer_init(void)
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{
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u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
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EP93XX_TIMER123_CONTROL_CLKSEL;
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arch_gettimeoffset = ep93xx_gettimeoffset;
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/* Enable periodic HZ timer. */
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__raw_writel(tmode, EP93XX_TIMER1_CONTROL);
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__raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
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__raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
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EP93XX_TIMER1_CONTROL);
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/* Enable lost jiffy timer. */
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__raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
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EP93XX_TIMER4_VALUE_HIGH);
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setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
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}
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