ARM: dts: vexpress: Support GICC_DIR operations
The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts. After this change the system supports split priority drop and interrupt deactivation. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> [sudeep.holla@arm.com: included same fix for tc1 platform too] Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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@ -81,7 +81,7 @@
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x1000>,
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<0 0x2c002000 0 0x2000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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@ -131,7 +131,7 @@
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0x2c001000 0 0x1000>,
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<0 0x2c002000 0 0x1000>,
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<0 0x2c002000 0 0x2000>,
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<0 0x2c004000 0 0x2000>,
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<0 0x2c006000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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