clk: qoriq: add more divider clocks support
More divider clocks are needed by IP. So enlarge the PLL divider array to accommodate more divider clocks. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -78,6 +78,7 @@ second cell is the clock index for the specified type.
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2 hwaccel index (n in CLKCGnHWACSR)
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3 fman 0 for fm1, 1 for fm2
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4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
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4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
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5 coreclk must be 0
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3. Example
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@ -41,7 +41,7 @@ struct clockgen_pll_div {
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};
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struct clockgen_pll {
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struct clockgen_pll_div div[4];
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struct clockgen_pll_div div[8];
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};
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#define CLKSEL_VALID 1
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@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
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struct clk *clk;
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int ret;
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/*
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* For platform PLL, there are 8 divider clocks.
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* For core PLL, there are 4 divider clocks at most.
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*/
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if (idx != PLATFORM_PLL && i >= 4)
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break;
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snprintf(pll->div[i].name, sizeof(pll->div[i].name),
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"cg-pll%d-div%d", idx, i + 1);
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