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@ -60,18 +60,18 @@ static void ivtv_pio_work_handler(struct ivtv *itv)
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buf = list_entry(s->q_dma.list.next, struct ivtv_buffer, list);
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list_for_each(p, &s->q_dma.list) {
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struct ivtv_buffer *buf = list_entry(p, struct ivtv_buffer, list);
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u32 size = s->PIOarray[i].size & 0x3ffff;
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u32 size = s->sg_processing[i].size & 0x3ffff;
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/* Copy the data from the card to the buffer */
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if (s->type == IVTV_DEC_STREAM_TYPE_VBI) {
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memcpy_fromio(buf->buf, itv->dec_mem + s->PIOarray[i].src - IVTV_DECODER_OFFSET, size);
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memcpy_fromio(buf->buf, itv->dec_mem + s->sg_processing[i].src - IVTV_DECODER_OFFSET, size);
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}
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else {
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memcpy_fromio(buf->buf, itv->enc_mem + s->PIOarray[i].src, size);
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memcpy_fromio(buf->buf, itv->enc_mem + s->sg_processing[i].src, size);
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}
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if (s->PIOarray[i].size & 0x80000000)
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break;
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i++;
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if (i == s->sg_processing_size)
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break;
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}
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write_reg(IVTV_IRQ_ENC_PIO_COMPLETE, 0x44);
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}
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@ -105,7 +105,7 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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u32 offset, size;
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u32 UVoffset = 0, UVsize = 0;
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int skip_bufs = s->q_predma.buffers;
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int idx = s->SG_length;
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int idx = s->sg_pending_size;
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int rc;
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/* sanity checks */
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@ -123,7 +123,7 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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case IVTV_ENC_STREAM_TYPE_MPG:
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offset = data[1];
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size = data[2];
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s->dma_pts = 0;
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s->pending_pts = 0;
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break;
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case IVTV_ENC_STREAM_TYPE_YUV:
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@ -131,13 +131,13 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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size = data[2];
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UVoffset = data[3];
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UVsize = data[4];
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s->dma_pts = ((u64) data[5] << 32) | data[6];
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s->pending_pts = ((u64) data[5] << 32) | data[6];
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break;
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case IVTV_ENC_STREAM_TYPE_PCM:
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offset = data[1] + 12;
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size = data[2] - 12;
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s->dma_pts = read_dec(offset - 8) |
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s->pending_pts = read_dec(offset - 8) |
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((u64)(read_dec(offset - 12)) << 32);
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if (itv->has_cx23415)
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offset += IVTV_DECODER_OFFSET;
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@ -150,13 +150,13 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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IVTV_DEBUG_INFO("VBI offset == 0\n");
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return -1;
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}
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s->dma_pts = read_enc(offset - 4) | ((u64)read_enc(offset - 8) << 32);
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s->pending_pts = read_enc(offset - 4) | ((u64)read_enc(offset - 8) << 32);
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break;
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case IVTV_DEC_STREAM_TYPE_VBI:
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size = read_dec(itv->vbi.dec_start + 4) + 8;
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offset = read_dec(itv->vbi.dec_start) + itv->vbi.dec_start;
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s->dma_pts = 0;
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s->pending_pts = 0;
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offset += IVTV_DECODER_OFFSET;
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break;
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default:
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@ -165,17 +165,17 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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}
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/* if this is the start of the DMA then fill in the magic cookie */
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if (s->SG_length == 0) {
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if (s->sg_pending_size == 0) {
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if (itv->has_cx23415 && (s->type == IVTV_ENC_STREAM_TYPE_PCM ||
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s->type == IVTV_DEC_STREAM_TYPE_VBI)) {
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s->dma_backup = read_dec(offset - IVTV_DECODER_OFFSET);
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s->pending_backup = read_dec(offset - IVTV_DECODER_OFFSET);
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write_dec_sync(cpu_to_le32(DMA_MAGIC_COOKIE), offset - IVTV_DECODER_OFFSET);
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}
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else {
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s->dma_backup = read_enc(offset);
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s->pending_backup = read_enc(offset);
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write_enc_sync(cpu_to_le32(DMA_MAGIC_COOKIE), offset);
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}
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s->dma_offset = offset;
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s->pending_offset = offset;
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}
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bytes_needed = size;
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@ -202,7 +202,7 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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}
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s->buffers_stolen = rc;
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/* got the buffers, now fill in SGarray (DMA) */
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/* got the buffers, now fill in sg_pending */
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buf = list_entry(s->q_predma.list.next, struct ivtv_buffer, list);
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memset(buf->buf, 0, 128);
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list_for_each(p, &s->q_predma.list) {
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@ -210,9 +210,9 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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if (skip_bufs-- > 0)
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continue;
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s->SGarray[idx].dst = cpu_to_le32(buf->dma_handle);
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s->SGarray[idx].src = cpu_to_le32(offset);
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s->SGarray[idx].size = cpu_to_le32(s->buf_size);
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s->sg_pending[idx].dst = buf->dma_handle;
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s->sg_pending[idx].src = offset;
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s->sg_pending[idx].size = s->buf_size;
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buf->bytesused = (size < s->buf_size) ? size : s->buf_size;
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buf->dma_xfer_cnt = s->dma_xfer_cnt;
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@ -230,7 +230,7 @@ static int stream_enc_dma_append(struct ivtv_stream *s, u32 data[CX2341X_MBOX_MA
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}
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idx++;
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}
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s->SG_length = idx;
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s->sg_pending_size = idx;
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return 0;
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}
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@ -332,9 +332,9 @@ void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock)
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offset = uv_offset;
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y_done = 1;
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}
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s->SGarray[idx].src = cpu_to_le32(buf->dma_handle);
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s->SGarray[idx].dst = cpu_to_le32(offset);
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s->SGarray[idx].size = cpu_to_le32(buf->bytesused);
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s->sg_pending[idx].src = buf->dma_handle;
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s->sg_pending[idx].dst = offset;
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s->sg_pending[idx].size = buf->bytesused;
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offset += buf->bytesused;
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bytes_written += buf->bytesused;
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@ -343,10 +343,7 @@ void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock)
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ivtv_buf_sync_for_device(s, buf);
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idx++;
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}
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s->SG_length = idx;
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/* Mark last buffer size for Interrupt flag */
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s->SGarray[s->SG_length - 1].size |= cpu_to_le32(0x80000000);
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s->sg_pending_size = idx;
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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@ -362,6 +359,34 @@ void ivtv_dma_stream_dec_prepare(struct ivtv_stream *s, u32 offset, int lock)
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spin_unlock_irqrestore(&itv->dma_reg_lock, flags);
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}
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static void ivtv_dma_enc_start_xfer(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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s->sg_dma->src = cpu_to_le32(s->sg_processing[s->sg_processed].src);
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s->sg_dma->dst = cpu_to_le32(s->sg_processing[s->sg_processed].dst);
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s->sg_dma->size = cpu_to_le32(s->sg_processing[s->sg_processed].size | 0x80000000);
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s->sg_processed++;
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
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}
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static void ivtv_dma_dec_start_xfer(struct ivtv_stream *s)
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{
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struct ivtv *itv = s->itv;
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s->sg_dma->src = cpu_to_le32(s->sg_processing[s->sg_processed].src);
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s->sg_dma->dst = cpu_to_le32(s->sg_processing[s->sg_processed].dst);
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s->sg_dma->size = cpu_to_le32(s->sg_processing[s->sg_processed].size | 0x80000000);
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s->sg_processed++;
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->sg_handle, IVTV_REG_DECDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER);
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}
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/* start the encoder DMA */
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static void ivtv_dma_enc_start(struct ivtv_stream *s)
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{
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@ -375,8 +400,7 @@ static void ivtv_dma_enc_start(struct ivtv_stream *s)
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ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
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if (ivtv_use_dma(s))
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s->SGarray[s->SG_length - 1].size =
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cpu_to_le32(le32_to_cpu(s->SGarray[s->SG_length - 1].size) + 256);
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s->sg_pending[s->sg_pending_size - 1].size += 256;
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/* If this is an MPEG stream, and VBI data is also pending, then append the
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VBI DMA to the MPEG DMA and transfer both sets of data at once.
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@ -387,45 +411,39 @@ static void ivtv_dma_enc_start(struct ivtv_stream *s)
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sure we only use the MPEG DMA to transfer the VBI DMA if both are in
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use. This way no conflicts occur. */
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clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags);
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if (s->type == IVTV_ENC_STREAM_TYPE_MPG && s_vbi->SG_length &&
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s->SG_length + s_vbi->SG_length <= s->buffers) {
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if (s->type == IVTV_ENC_STREAM_TYPE_MPG && s_vbi->sg_pending_size &&
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s->sg_pending_size + s_vbi->sg_pending_size <= s->buffers) {
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ivtv_queue_move(s_vbi, &s_vbi->q_predma, NULL, &s_vbi->q_dma, s_vbi->q_predma.bytesused);
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if (ivtv_use_dma(s_vbi))
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s_vbi->SGarray[s_vbi->SG_length - 1].size = cpu_to_le32(le32_to_cpu(s_vbi->SGarray[s->SG_length - 1].size) + 256);
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for (i = 0; i < s_vbi->SG_length; i++) {
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s->SGarray[s->SG_length++] = s_vbi->SGarray[i];
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s_vbi->sg_pending[s_vbi->sg_pending_size - 1].size += 256;
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for (i = 0; i < s_vbi->sg_pending_size; i++) {
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s->sg_pending[s->sg_pending_size++] = s_vbi->sg_pending[i];
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}
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itv->vbi.dma_offset = s_vbi->dma_offset;
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s_vbi->SG_length = 0;
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s_vbi->dma_offset = s_vbi->pending_offset;
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s_vbi->sg_pending_size = 0;
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s_vbi->dma_xfer_cnt++;
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set_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags);
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IVTV_DEBUG_HI_DMA("include DMA for %s\n", s->name);
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}
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/* Mark last buffer size for Interrupt flag */
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s->SGarray[s->SG_length - 1].size |= cpu_to_le32(0x80000000);
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s->dma_xfer_cnt++;
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if (s->type == IVTV_ENC_STREAM_TYPE_VBI)
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set_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
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else
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clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
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memcpy(s->sg_processing, s->sg_pending, sizeof(struct ivtv_sg_element) * s->sg_pending_size);
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s->sg_processing_size = s->sg_pending_size;
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s->sg_pending_size = 0;
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s->sg_processed = 0;
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s->dma_offset = s->pending_offset;
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s->dma_backup = s->pending_backup;
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s->dma_pts = s->pending_pts;
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if (ivtv_use_pio(s)) {
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for (i = 0; i < s->SG_length; i++) {
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s->PIOarray[i].src = le32_to_cpu(s->SGarray[i].src);
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s->PIOarray[i].size = le32_to_cpu(s->SGarray[i].size);
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}
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set_bit(IVTV_F_I_WORK_HANDLER_PIO, &itv->i_flags);
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set_bit(IVTV_F_I_HAVE_WORK, &itv->i_flags);
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set_bit(IVTV_F_I_PIO, &itv->i_flags);
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itv->cur_pio_stream = s->type;
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}
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else {
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/* Sync Hardware SG List of buffers */
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ivtv_stream_sync_for_device(s);
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write_reg(s->SG_handle, IVTV_REG_ENCDMAADDR);
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write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER);
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itv->dma_retries = 0;
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ivtv_dma_enc_start_xfer(s);
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set_bit(IVTV_F_I_DMA, &itv->i_flags);
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itv->cur_dma_stream = s->type;
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itv->dma_timer.expires = jiffies + msecs_to_jiffies(100);
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|
@ -439,10 +457,15 @@ static void ivtv_dma_dec_start(struct ivtv_stream *s)
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if (s->q_predma.bytesused)
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ivtv_queue_move(s, &s->q_predma, NULL, &s->q_dma, s->q_predma.bytesused);
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s->dma_xfer_cnt++;
|
|
|
|
|
memcpy(s->sg_processing, s->sg_pending, sizeof(struct ivtv_sg_element) * s->sg_pending_size);
|
|
|
|
|
s->sg_processing_size = s->sg_pending_size;
|
|
|
|
|
s->sg_pending_size = 0;
|
|
|
|
|
s->sg_processed = 0;
|
|
|
|
|
|
|
|
|
|
IVTV_DEBUG_HI_DMA("start DMA for %s\n", s->name);
|
|
|
|
|
/* put SG Handle into register 0x0c */
|
|
|
|
|
write_reg(s->SG_handle, IVTV_REG_DECDMAADDR);
|
|
|
|
|
write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER);
|
|
|
|
|
itv->dma_retries = 0;
|
|
|
|
|
ivtv_dma_dec_start_xfer(s);
|
|
|
|
|
set_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
|
|
|
itv->cur_dma_stream = s->type;
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|
|
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|
itv->dma_timer.expires = jiffies + msecs_to_jiffies(100);
|
|
|
|
@ -453,27 +476,42 @@ static void ivtv_irq_dma_read(struct ivtv *itv)
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|
|
|
{
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|
|
|
|
struct ivtv_stream *s = NULL;
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|
|
|
|
struct ivtv_buffer *buf;
|
|
|
|
|
int hw_stream_type;
|
|
|
|
|
int hw_stream_type = 0;
|
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|
|
|
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|
|
|
|
IVTV_DEBUG_HI_IRQ("DEC DMA READ\n");
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|
|
del_timer(&itv->dma_timer);
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|
|
|
if (read_reg(IVTV_REG_DMASTATUS) & 0x14) {
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|
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|
IVTV_DEBUG_WARN("DEC DMA ERROR %x\n", read_reg(IVTV_REG_DMASTATUS));
|
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|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
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|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0) {
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|
|
|
|
del_timer(&itv->dma_timer);
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|
|
|
|
return;
|
|
|
|
|
}
|
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|
|
|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
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|
|
|
|
if (test_bit(IVTV_F_I_DEC_YUV, &itv->i_flags)) {
|
|
|
|
|
s = &itv->streams[IVTV_DEC_STREAM_TYPE_YUV];
|
|
|
|
|
hw_stream_type = 2;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
s = &itv->streams[IVTV_DEC_STREAM_TYPE_MPG];
|
|
|
|
|
hw_stream_type = 0;
|
|
|
|
|
}
|
|
|
|
|
IVTV_DEBUG_HI_DMA("DEC DATA READ %s: %d\n", s->name, s->q_dma.bytesused);
|
|
|
|
|
|
|
|
|
|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
|
|
|
|
|
s = &itv->streams[itv->cur_dma_stream];
|
|
|
|
|
ivtv_stream_sync_for_cpu(s);
|
|
|
|
|
|
|
|
|
|
if (read_reg(IVTV_REG_DMASTATUS) & 0x14) {
|
|
|
|
|
IVTV_DEBUG_WARN("DEC DMA ERROR %x (xfer %d of %d, retry %d)\n",
|
|
|
|
|
read_reg(IVTV_REG_DMASTATUS),
|
|
|
|
|
s->sg_processed, s->sg_processing_size, itv->dma_retries);
|
|
|
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
|
|
|
if (itv->dma_retries == 3) {
|
|
|
|
|
itv->dma_retries = 0;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
/* Retry, starting with the first xfer segment.
|
|
|
|
|
Just retrying the current segment is not sufficient. */
|
|
|
|
|
s->sg_processed = 0;
|
|
|
|
|
itv->dma_retries++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (s->sg_processed < s->sg_processing_size) {
|
|
|
|
|
/* DMA next buffer */
|
|
|
|
|
ivtv_dma_dec_start_xfer(s);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (s->type == IVTV_DEC_STREAM_TYPE_YUV)
|
|
|
|
|
hw_stream_type = 2;
|
|
|
|
|
IVTV_DEBUG_HI_DMA("DEC DATA READ %s: %d\n", s->name, s->q_dma.bytesused);
|
|
|
|
|
|
|
|
|
|
/* For some reason must kick the firmware, like PIO mode,
|
|
|
|
|
I think this tells the firmware we are done and the size
|
|
|
|
|
of the xfer so it can calculate what we need next.
|
|
|
|
@ -490,6 +528,7 @@ static void ivtv_irq_dma_read(struct ivtv *itv)
|
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|
|
|
}
|
|
|
|
|
wake_up(&s->waitq);
|
|
|
|
|
}
|
|
|
|
|
del_timer(&itv->dma_timer);
|
|
|
|
|
clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
|
|
|
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
|
|
|
itv->cur_dma_stream = -1;
|
|
|
|
@ -501,33 +540,44 @@ static void ivtv_irq_enc_dma_complete(struct ivtv *itv)
|
|
|
|
|
u32 data[CX2341X_MBOX_MAX_DATA];
|
|
|
|
|
struct ivtv_stream *s;
|
|
|
|
|
|
|
|
|
|
del_timer(&itv->dma_timer);
|
|
|
|
|
ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
|
|
|
|
|
IVTV_DEBUG_HI_IRQ("ENC DMA COMPLETE %x %d\n", data[0], data[1]);
|
|
|
|
|
if (test_and_clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags))
|
|
|
|
|
data[1] = 3;
|
|
|
|
|
else if (data[1] > 2)
|
|
|
|
|
IVTV_DEBUG_HI_IRQ("ENC DMA COMPLETE %x %d (%d)\n", data[0], data[1], itv->cur_dma_stream);
|
|
|
|
|
if (itv->cur_dma_stream < 0) {
|
|
|
|
|
del_timer(&itv->dma_timer);
|
|
|
|
|
return;
|
|
|
|
|
s = &itv->streams[ivtv_stream_map[data[1]]];
|
|
|
|
|
if (data[0] & 0x18) {
|
|
|
|
|
IVTV_DEBUG_WARN("ENC DMA ERROR %x\n", data[0]);
|
|
|
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
|
|
|
ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, data[1]);
|
|
|
|
|
}
|
|
|
|
|
s->SG_length = 0;
|
|
|
|
|
s = &itv->streams[itv->cur_dma_stream];
|
|
|
|
|
ivtv_stream_sync_for_cpu(s);
|
|
|
|
|
|
|
|
|
|
if (data[0] & 0x18) {
|
|
|
|
|
IVTV_DEBUG_WARN("ENC DMA ERROR %x (offset %08x, xfer %d of %d, retry %d)\n", data[0],
|
|
|
|
|
s->dma_offset, s->sg_processed, s->sg_processing_size, itv->dma_retries);
|
|
|
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
|
|
|
if (itv->dma_retries == 3) {
|
|
|
|
|
itv->dma_retries = 0;
|
|
|
|
|
}
|
|
|
|
|
else {
|
|
|
|
|
/* Retry, starting with the first xfer segment.
|
|
|
|
|
Just retrying the current segment is not sufficient. */
|
|
|
|
|
s->sg_processed = 0;
|
|
|
|
|
itv->dma_retries++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (s->sg_processed < s->sg_processing_size) {
|
|
|
|
|
/* DMA next buffer */
|
|
|
|
|
ivtv_dma_enc_start_xfer(s);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
del_timer(&itv->dma_timer);
|
|
|
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
|
|
|
itv->cur_dma_stream = -1;
|
|
|
|
|
dma_post(s);
|
|
|
|
|
ivtv_stream_sync_for_cpu(s);
|
|
|
|
|
if (test_and_clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags)) {
|
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
|
|
s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
|
|
|
|
|
tmp = s->dma_offset;
|
|
|
|
|
s->dma_offset = itv->vbi.dma_offset;
|
|
|
|
|
dma_post(s);
|
|
|
|
|
s->dma_offset = tmp;
|
|
|
|
|
}
|
|
|
|
|
s->sg_processing_size = 0;
|
|
|
|
|
s->sg_processed = 0;
|
|
|
|
|
wake_up(&itv->dma_waitq);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
@ -541,8 +591,7 @@ static void ivtv_irq_enc_pio_complete(struct ivtv *itv)
|
|
|
|
|
}
|
|
|
|
|
s = &itv->streams[itv->cur_pio_stream];
|
|
|
|
|
IVTV_DEBUG_HI_IRQ("ENC PIO COMPLETE %s\n", s->name);
|
|
|
|
|
s->SG_length = 0;
|
|
|
|
|
clear_bit(IVTV_F_I_ENC_VBI, &itv->i_flags);
|
|
|
|
|
s->sg_pending_size = 0;
|
|
|
|
|
clear_bit(IVTV_F_I_PIO, &itv->i_flags);
|
|
|
|
|
itv->cur_pio_stream = -1;
|
|
|
|
|
dma_post(s);
|
|
|
|
@ -554,13 +603,8 @@ static void ivtv_irq_enc_pio_complete(struct ivtv *itv)
|
|
|
|
|
ivtv_vapi(itv, CX2341X_ENC_SCHED_DMA_TO_HOST, 3, 0, 0, 2);
|
|
|
|
|
clear_bit(IVTV_F_I_PIO, &itv->i_flags);
|
|
|
|
|
if (test_and_clear_bit(IVTV_F_S_DMA_HAS_VBI, &s->s_flags)) {
|
|
|
|
|
u32 tmp;
|
|
|
|
|
|
|
|
|
|
s = &itv->streams[IVTV_ENC_STREAM_TYPE_VBI];
|
|
|
|
|
tmp = s->dma_offset;
|
|
|
|
|
s->dma_offset = itv->vbi.dma_offset;
|
|
|
|
|
dma_post(s);
|
|
|
|
|
s->dma_offset = tmp;
|
|
|
|
|
}
|
|
|
|
|
wake_up(&itv->dma_waitq);
|
|
|
|
|
}
|
|
|
|
@ -572,19 +616,23 @@ static void ivtv_irq_dma_err(struct ivtv *itv)
|
|
|
|
|
del_timer(&itv->dma_timer);
|
|
|
|
|
ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data);
|
|
|
|
|
IVTV_DEBUG_WARN("DMA ERROR %08x %08x %08x %d\n", data[0], data[1],
|
|
|
|
|
read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
|
|
|
|
|
read_reg(IVTV_REG_DMASTATUS), itv->cur_dma_stream);
|
|
|
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
|
|
|
if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) &&
|
|
|
|
|
itv->cur_dma_stream >= 0 && itv->cur_dma_stream < IVTV_MAX_STREAMS) {
|
|
|
|
|
struct ivtv_stream *s = &itv->streams[itv->cur_dma_stream];
|
|
|
|
|
|
|
|
|
|
/* retry */
|
|
|
|
|
write_reg(read_reg(IVTV_REG_DMASTATUS) & 3, IVTV_REG_DMASTATUS);
|
|
|
|
|
if (s->type >= IVTV_DEC_STREAM_TYPE_MPG)
|
|
|
|
|
ivtv_dma_dec_start(s);
|
|
|
|
|
else
|
|
|
|
|
ivtv_dma_enc_start(s);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
if (test_bit(IVTV_F_I_UDMA, &itv->i_flags)) {
|
|
|
|
|
ivtv_udma_start(itv);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
clear_bit(IVTV_F_I_UDMA, &itv->i_flags);
|
|
|
|
|
clear_bit(IVTV_F_I_DMA, &itv->i_flags);
|
|
|
|
|
itv->cur_dma_stream = -1;
|
|
|
|
@ -628,14 +676,14 @@ static void ivtv_irq_enc_vbi_cap(struct ivtv *itv)
|
|
|
|
|
DMA the data. Since at most four VBI DMA buffers are available,
|
|
|
|
|
we just drop the old requests when there are already three
|
|
|
|
|
requests queued. */
|
|
|
|
|
if (s->SG_length > 2) {
|
|
|
|
|
if (s->sg_pending_size > 2) {
|
|
|
|
|
struct list_head *p;
|
|
|
|
|
list_for_each(p, &s->q_predma.list) {
|
|
|
|
|
struct ivtv_buffer *buf = list_entry(p, struct ivtv_buffer, list);
|
|
|
|
|
ivtv_buf_sync_for_cpu(s, buf);
|
|
|
|
|
}
|
|
|
|
|
ivtv_queue_move(s, &s->q_predma, NULL, &s->q_free, 0);
|
|
|
|
|
s->SG_length = 0;
|
|
|
|
|
s->sg_pending_size = 0;
|
|
|
|
|
}
|
|
|
|
|
/* if we can append the data, and the MPEG stream isn't capturing,
|
|
|
|
|
then start a DMA request for just the VBI data. */
|
|
|
|
|