net: phy: dp83867: add workaround for incorrect RX_CTRL pin strap
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017, advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not supported (see note below Table 5 (4-Level Strap Pins)). There are some boards which have the pin strapped this way and need software workaround suggested by the data manual. Bit[7] of Configuration Register 4 (address 0x0031) must be cleared to 0. This ensures proper operation of the PHY. Implement driver support for device-tree property meant to advertise the wrong strapping. [1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> [nsekhar@ti.com: rebase to mainline, code simplification] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -91,6 +91,7 @@ struct dp83867_private {
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int fifo_depth;
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int io_impedance;
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int port_mirroring;
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bool rxctrl_strap_quirk;
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};
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static int dp83867_ack_interrupt(struct phy_device *phydev)
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@ -164,6 +165,9 @@ static int dp83867_of_init(struct phy_device *phydev)
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else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
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dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
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dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
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"ti,dp83867-rxctrl-strap-quirk");
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ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
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&dp83867->rx_id_delay);
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if (ret &&
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@ -214,6 +218,13 @@ static int dp83867_config_init(struct phy_device *phydev)
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dp83867 = (struct dp83867_private *)phydev->priv;
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}
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/* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
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if (dp83867->rxctrl_strap_quirk) {
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val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
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val &= ~BIT(7);
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phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
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}
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if (phy_interface_is_rgmii(phydev)) {
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val = phy_read(phydev, MII_DP83867_PHYCTRL);
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if (val < 0)
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