clocksource/drivers/timer-milbeaut: Cleanup common register accesses
Aggregate common register accesses into shared functions for maintainability. Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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@ -26,8 +26,8 @@
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#define MLB_TMR_TMCSR_CSL_DIV2 0
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#define MLB_TMR_DIV_CNT 2
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#define MLB_TMR_SRC_CH (1)
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#define MLB_TMR_EVT_CH (0)
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#define MLB_TMR_SRC_CH 1
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#define MLB_TMR_EVT_CH 0
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#define MLB_TMR_SRC_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_SRC_CH)
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#define MLB_TMR_EVT_CH_OFS (MLB_TMR_REGSZPCH * MLB_TMR_EVT_CH)
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@ -43,6 +43,8 @@
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#define MLB_TMR_EVT_TMRLR2_OFS (MLB_TMR_EVT_CH_OFS + MLB_TMR_TMRLR2_OFS)
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#define MLB_TIMER_RATING 500
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#define MLB_TIMER_ONESHOT 0
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#define MLB_TIMER_PERIODIC 1
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static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
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{
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@ -59,38 +61,53 @@ static irqreturn_t mlb_timer_interrupt(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static void mlb_evt_timer_start(struct timer_of *to, bool periodic)
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{
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u32 val = MLB_TMR_TMCSR_CSL_DIV2;
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val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
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if (periodic)
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val |= MLB_TMR_TMCSR_RELD;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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}
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static void mlb_evt_timer_stop(struct timer_of *to)
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{
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u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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val &= ~MLB_TMR_TMCSR_CNTE;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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}
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static void mlb_evt_timer_register_count(struct timer_of *to, unsigned long cnt)
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{
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writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
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}
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static int mlb_set_state_periodic(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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u32 val = MLB_TMR_TMCSR_CSL_DIV2;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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writel_relaxed(to->of_clk.period, timer_of_base(to) +
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MLB_TMR_EVT_TMRLR1_OFS);
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val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE |
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MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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mlb_evt_timer_stop(to);
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mlb_evt_timer_register_count(to, to->of_clk.period);
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mlb_evt_timer_start(to, MLB_TIMER_PERIODIC);
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return 0;
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}
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static int mlb_set_state_oneshot(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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u32 val = MLB_TMR_TMCSR_CSL_DIV2;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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val |= MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG | MLB_TMR_TMCSR_INTE;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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mlb_evt_timer_stop(to);
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mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
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return 0;
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}
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static int mlb_set_state_shutdown(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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u32 val = MLB_TMR_TMCSR_CSL_DIV2;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
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mlb_evt_timer_stop(to);
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return 0;
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}
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@ -99,22 +116,21 @@ static int mlb_clkevt_next_event(unsigned long event,
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{
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struct timer_of *to = to_timer_of(clk);
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writel_relaxed(event, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
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writel_relaxed(MLB_TMR_TMCSR_CSL_DIV2 |
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MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_INTE |
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MLB_TMR_TMCSR_TRG, timer_of_base(to) +
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MLB_TMR_EVT_TMCSR_OFS);
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mlb_evt_timer_stop(to);
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mlb_evt_timer_register_count(to, event);
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mlb_evt_timer_start(to, MLB_TIMER_ONESHOT);
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return 0;
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}
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static int mlb_config_clock_source(struct timer_of *to)
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{
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writel_relaxed(0, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
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writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMR_OFS);
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u32 val = MLB_TMR_TMCSR_CSL_DIV2;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
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writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
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writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
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writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) +
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MLB_TMR_SRC_TMCSR_OFS);
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val |= MLB_TMR_TMCSR_RELD | MLB_TMR_TMCSR_CNTE | MLB_TMR_TMCSR_TRG;
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writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
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return 0;
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}
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