sh: Get SH-5 caches working again post-unification.
A number of cleanups to get the SH-5 cache management code in line with the rest of the SH backend. Signed-off-by: Paul Mundt <lethal@linux-sh.org>wifi-calibration
Paul Mundt
parent
5c8f82c649
commit
38350e0a00
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@ -20,19 +20,18 @@ int __init detect_cpu_and_cache_system(void)
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{
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unsigned long long cir;
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/* Do peeks in real mode to avoid having to set up a mapping for the
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WPC registers. On SH5-101 cut2, such a mapping would be exposed to
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an address translation erratum which would make it hard to set up
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correctly. */
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/*
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* Do peeks in real mode to avoid having to set up a mapping for
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* the WPC registers. On SH5-101 cut2, such a mapping would be
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* exposed to an address translation erratum which would make it
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* hard to set up correctly.
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*/
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cir = peek_real_address_q(0x0d000008);
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if ((cir & 0xffff) == 0x5103) {
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if ((cir & 0xffff) == 0x5103)
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boot_cpu_data.type = CPU_SH5_103;
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} else if (((cir >> 32) & 0xffff) == 0x51e2) {
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else if (((cir >> 32) & 0xffff) == 0x51e2)
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/* CPU.VCR aliased at CIR address on SH5-101 */
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boot_cpu_data.type = CPU_SH5_101;
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} else {
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boot_cpu_data.type = CPU_SH_NONE;
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}
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/*
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* First, setup some sane values for the I-cache.
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@ -40,37 +39,33 @@ int __init detect_cpu_and_cache_system(void)
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boot_cpu_data.icache.ways = 4;
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boot_cpu_data.icache.sets = 256;
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boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
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#if 0
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/*
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* FIXME: This can probably be cleaned up a bit as well.. for example,
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* do we really need the way shift _and_ the way_step_shift ?? Judging
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* by the existing code, I would guess no.. is there any valid reason
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* why we need to be tracking this around?
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*/
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boot_cpu_data.icache.way_shift = 13;
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boot_cpu_data.icache.way_incr = (1 << 13);
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boot_cpu_data.icache.entry_shift = 5;
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boot_cpu_data.icache.set_shift = 4;
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boot_cpu_data.icache.way_step_shift = 16;
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boot_cpu_data.icache.asid_shift = 2;
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/*
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* way offset = cache size / associativity, so just don't factor in
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* associativity in the first place..
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*/
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boot_cpu_data.icache.way_ofs = boot_cpu_data.icache.sets *
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boot_cpu_data.icache.linesz;
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boot_cpu_data.icache.asid_mask = 0x3fc;
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boot_cpu_data.icache.idx_mask = 0x1fe0;
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boot_cpu_data.icache.epn_mask = 0xffffe000;
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#endif
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boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets *
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boot_cpu_data.icache.linesz;
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boot_cpu_data.icache.entry_mask = 0x1fe0;
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boot_cpu_data.icache.flags = 0;
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/* A trivial starting point.. */
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memcpy(&boot_cpu_data.dcache,
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&boot_cpu_data.icache, sizeof(struct cache_info));
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/*
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* Next, setup some sane values for the D-cache.
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*
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* On the SH5, these are pretty consistent with the I-cache settings,
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* so we just copy over the existing definitions.. these can be fixed
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* up later, especially if we add runtime CPU probing.
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*
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* Though in the meantime it saves us from having to duplicate all of
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* the above definitions..
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*/
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boot_cpu_data.dcache = boot_cpu_data.icache;
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/*
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* Setup any cache-related flags here
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*/
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#if defined(CONFIG_CACHE_WRITETHROUGH)
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set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags));
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#elif defined(CONFIG_CACHE_WRITEBACK)
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set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
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#endif
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return 0;
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}
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File diff suppressed because it is too large
Load Diff
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@ -3,8 +3,6 @@
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#ifndef __ASSEMBLY__
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#include <asm/page.h>
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struct vm_area_struct;
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struct page;
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struct mm_struct;
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@ -27,7 +25,7 @@ extern void flush_icache_user_range(struct vm_area_struct *vma,
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_icache_page(vma, page) do { } while (0)
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#define p3_cache_init() do { } while (0)
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void p3_cache_init(void);
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#endif /* __ASSEMBLY__ */
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@ -66,6 +66,9 @@ static inline void set_asid(unsigned long asid)
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: "=r" (sr), "=r" (pc) : "0" (sr));
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}
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/* arch/sh/kernel/cpu/sh5/entry.S */
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extern unsigned long switch_and_save_asid(unsigned long new_asid);
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/* No spare register to twiddle, so use a software cache */
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extern pgd_t *mmu_pdtp_cache;
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@ -55,11 +55,14 @@ extern void clear_page(void *to);
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extern void copy_page(void *to, void *from);
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#if !defined(CONFIG_CACHE_OFF) && defined(CONFIG_MMU) && \
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(defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB))
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(defined(CONFIG_CPU_SH5) || defined(CONFIG_CPU_SH4) || \
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defined(CONFIG_SH7705_CACHE_32KB))
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struct page;
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struct vm_area_struct;
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extern void clear_user_page(void *to, unsigned long address, struct page *page);
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#ifdef CONFIG_CPU_SH4
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extern void copy_user_page(void *to, void *from, unsigned long address,
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struct page *page);
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#if defined(CONFIG_CPU_SH4)
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extern void copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr, struct vm_area_struct *vma);
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#define __HAVE_ARCH_COPY_USER_HIGHPAGE
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