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gpio: Fix checkpatch.pl issues 

This patch fixes some issues given by checkpatch. Fixes include
bracket placement, spacing and indenting.

Signed-off-by: Daniel Lockyer <thisisdaniellockyer@gmail.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
steinar/wifi_calib_4_9_kernel
Daniel Lockyer 2015-06-10 14:26:27 +01:00 committed by Linus Walleij
parent 84f28998cc
commit 38e003f4b5
5 changed files with 13 additions and 16 deletions
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3
drivers/gpio/gpio-altera.c
View File

@ -107,7 +107,8 @@ static int altera_gpio_irq_set_type(struct irq_data *d,
return -EINVAL;
}
static unsigned int altera_gpio_irq_startup(struct irq_data *d) {
static unsigned int altera_gpio_irq_startup(struct irq_data *d)
{
altera_gpio_irq_unmask(d);
return 0;

3
drivers/gpio/gpio-crystalcove.c
View File

@ -95,9 +95,8 @@ static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
int reg;
if (gpio == 94) {
if (gpio == 94)
return GPIOPANELCTL;
}
if (reg_type == CTRL_IN) {
if (gpio < 8)

4
drivers/gpio/gpio-f7188x.c
View File

@ -172,7 +172,7 @@ static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
};
static struct f7188x_gpio_bank f71882_gpio_bank[] = {
F7188X_GPIO_BANK(0 , 8, 0xF0),
F7188X_GPIO_BANK(0, 8, 0xF0),
F7188X_GPIO_BANK(10, 8, 0xE0),
F7188X_GPIO_BANK(20, 8, 0xD0),
F7188X_GPIO_BANK(30, 4, 0xC0),
@ -180,7 +180,7 @@ static struct f7188x_gpio_bank f71882_gpio_bank[] = {
};
static struct f7188x_gpio_bank f71889_gpio_bank[] = {
F7188X_GPIO_BANK(0 , 7, 0xF0),
F7188X_GPIO_BANK(0, 7, 0xF0),
F7188X_GPIO_BANK(10, 7, 0xE0),
F7188X_GPIO_BANK(20, 8, 0xD0),
F7188X_GPIO_BANK(30, 8, 0xC0),

2
drivers/gpio/gpio-it8761e.c
View File

@ -123,7 +123,7 @@ static void it8761e_gpio_set(struct gpio_chip *gc,
curr_vals = inb(reg);
if (val)
outb(curr_vals | (1 << bit) , reg);
outb(curr_vals | (1 << bit), reg);
else
outb(curr_vals & ~(1 << bit), reg);

17
drivers/gpio/gpiolib.c
View File

@ -1309,9 +1309,8 @@ static void gpio_chip_set_multiple(struct gpio_chip *chip,
continue;
}
/* set outputs if the corresponding mask bit is set */
if (__test_and_clear_bit(i, mask)) {
if (__test_and_clear_bit(i, mask))
chip->set(chip, i, test_bit(i, bits));
}
}
}
}
@ -1329,9 +1328,9 @@ static void gpiod_set_array_value_priv(bool raw, bool can_sleep,
unsigned long bits[BITS_TO_LONGS(chip->ngpio)];
int count = 0;
if (!can_sleep) {
if (!can_sleep)
WARN_ON(chip->can_sleep);
}
memset(mask, 0, sizeof(mask));
do {
struct gpio_desc *desc = desc_array[i];
@ -1346,24 +1345,22 @@ static void gpiod_set_array_value_priv(bool raw, bool can_sleep,
* open drain and open source outputs are set individually
*/
if (test_bit(FLAG_OPEN_DRAIN, &desc->flags)) {
_gpio_set_open_drain_value(desc,value);
_gpio_set_open_drain_value(desc, value);
} else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) {
_gpio_set_open_source_value(desc, value);
} else {
__set_bit(hwgpio, mask);
if (value) {
if (value)
__set_bit(hwgpio, bits);
} else {
else
__clear_bit(hwgpio, bits);
}
count++;
}
i++;
} while ((i < array_size) && (desc_array[i]->chip == chip));
/* push collected bits to outputs */
if (count != 0) {
if (count != 0)
gpio_chip_set_multiple(chip, mask, bits);
}
}
}