Merge branch 'for_3.14/keystone-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into clk-next-keystone
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commit
391e3903e6
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@ -17,13 +17,14 @@ Required properties:
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- reg - pll control0 and pll multipler registers
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- reg-names : control and multiplier. The multiplier is applicable only for
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main pll clock
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- fixed-postdiv : fixed post divider value
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- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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for postdiv
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Example:
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mainpllclk: mainpllclk@2310110 {
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#clock-cells = <0>;
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compatible = "ti,keystone,main-pll-clock";
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clocks = <&refclkmain>;
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clocks = <&refclksys>;
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reg = <0x02620350 4>, <0x02310110 4>;
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reg-names = "control", "multiplier";
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fixed-postdiv = <2>;
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@ -32,11 +33,10 @@ Example:
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papllclk: papllclk@2620358 {
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#clock-cells = <0>;
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compatible = "ti,keystone,pll-clock";
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clocks = <&refclkmain>;
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clocks = <&refclkpass>;
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clock-output-names = "pa-pll-clk";
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reg = <0x02620358 4>;
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reg-names = "control";
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fixed-postdiv = <6>;
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};
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Required properties:
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@ -223,8 +223,7 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
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data->domain_base = of_iomap(node, i);
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if (!data->domain_base) {
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pr_err("%s: domain ioremap failed\n", __func__);
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iounmap(data->control_base);
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goto out;
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goto unmap_ctrl;
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}
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of_property_read_u32(node, "domain-id", &data->domain_id);
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@ -237,16 +236,21 @@ static void __init of_psc_clk_init(struct device_node *node, spinlock_t *lock)
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parent_name = of_clk_get_parent_name(node, 0);
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if (!parent_name) {
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pr_err("%s: Parent clock not found\n", __func__);
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goto out;
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goto unmap_domain;
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}
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clk = clk_register_psc(NULL, clk_name, parent_name, data, lock);
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if (clk) {
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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}
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pr_err("%s: error registering clk %s\n", __func__, node->name);
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unmap_domain:
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iounmap(data->domain_base);
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unmap_ctrl:
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iounmap(data->control_base);
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out:
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kfree(data);
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return;
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@ -24,6 +24,8 @@
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#define MAIN_PLLM_HIGH_MASK 0x7f000
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#define PLLM_HIGH_SHIFT 6
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#define PLLD_MASK 0x3f
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#define CLKOD_MASK 0x780000
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#define CLKOD_SHIFT 19
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/**
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* struct clk_pll_data - pll data structure
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@ -41,7 +43,10 @@
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* @pllm_upper_mask: multiplier upper mask
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* @pllm_upper_shift: multiplier upper shift
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* @plld_mask: divider mask
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* @postdiv: Post divider
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* @clkod_mask: output divider mask
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* @clkod_shift: output divider shift
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* @plld_mask: divider mask
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* @postdiv: Fixed post divider
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*/
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struct clk_pll_data {
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bool has_pllctrl;
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@ -53,6 +58,8 @@ struct clk_pll_data {
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u32 pllm_upper_mask;
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u32 pllm_upper_shift;
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u32 plld_mask;
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u32 clkod_mask;
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u32 clkod_shift;
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u32 postdiv;
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};
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@ -90,6 +97,12 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
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mult |= ((val & pll_data->pllm_upper_mask)
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>> pll_data->pllm_upper_shift);
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prediv = (val & pll_data->plld_mask);
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if (!pll_data->has_pllctrl)
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/* read post divider from od bits*/
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postdiv = ((val & pll_data->clkod_mask) >>
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pll_data->clkod_shift) + 1;
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else
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postdiv = pll_data->postdiv;
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rate /= (prediv + 1);
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@ -155,8 +168,11 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
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}
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parent_name = of_clk_get_parent_name(node, 0);
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if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv))
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goto out;
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if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) {
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/* assume the PLL has output divider register bits */
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pll_data->clkod_mask = CLKOD_MASK;
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pll_data->clkod_shift = CLKOD_SHIFT;
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}
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i = of_property_match_string(node, "reg-names", "control");
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pll_data->pll_ctl0 = of_iomap(node, i);
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