Merge branch 'spi-5.1' into spi-5.2 for stm32
This commit is contained in:
commit
3949ba3b37
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@ -1501,7 +1501,7 @@ static int spi_imx_transfer(struct spi_device *spi,
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/* flush rxfifo before transfer */
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while (spi_imx->devtype_data->rx_available(spi_imx))
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spi_imx->rx(spi_imx);
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readl(spi_imx->base + MXC_CSPIRXDATA);
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if (spi_imx->slave_mode)
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return spi_imx_pio_transfer_slave(spi, transfer);
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@ -271,7 +271,8 @@ static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
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/* Sets parity, interrupt mask */
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rspi_write8(rspi, 0x00, RSPI_SPCR2);
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/* Sets SPCMD */
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/* Resets sequencer */
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rspi_write8(rspi, 0, RSPI_SPSCR);
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rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
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rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
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@ -315,7 +316,8 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
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rspi_write8(rspi, 0x00, RSPI_SSLND);
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rspi_write8(rspi, 0x00, RSPI_SPND);
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/* Sets SPCMD */
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/* Resets sequencer */
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rspi_write8(rspi, 0, RSPI_SPSCR);
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rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
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rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
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@ -366,7 +368,8 @@ static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
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/* Sets buffer to allow normal operation */
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rspi_write8(rspi, 0x00, QSPI_SPBFCR);
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/* Sets SPCMD */
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/* Resets sequencer */
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rspi_write8(rspi, 0, RSPI_SPSCR);
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rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
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/* Sets RSPI mode */
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@ -868,28 +871,6 @@ static int qspi_transfer_one(struct spi_controller *ctlr,
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}
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}
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static int rspi_setup(struct spi_device *spi)
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{
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struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
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rspi->max_speed_hz = spi->max_speed_hz;
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rspi->spcmd = SPCMD_SSLKP;
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if (spi->mode & SPI_CPOL)
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rspi->spcmd |= SPCMD_CPOL;
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if (spi->mode & SPI_CPHA)
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rspi->spcmd |= SPCMD_CPHA;
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/* CMOS output mode and MOSI signal from previous transfer */
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rspi->sppcr = 0;
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if (spi->mode & SPI_LOOP)
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rspi->sppcr |= SPPCR_SPLP;
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set_config_register(rspi, 8);
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return 0;
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}
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static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
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{
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if (xfer->tx_buf)
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@ -959,8 +940,24 @@ static int rspi_prepare_message(struct spi_controller *ctlr,
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struct spi_message *msg)
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{
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struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
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struct spi_device *spi = msg->spi;
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int ret;
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rspi->max_speed_hz = spi->max_speed_hz;
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rspi->spcmd = SPCMD_SSLKP;
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if (spi->mode & SPI_CPOL)
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rspi->spcmd |= SPCMD_CPOL;
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if (spi->mode & SPI_CPHA)
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rspi->spcmd |= SPCMD_CPHA;
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/* CMOS output mode and MOSI signal from previous transfer */
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rspi->sppcr = 0;
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if (spi->mode & SPI_LOOP)
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rspi->sppcr |= SPPCR_SPLP;
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set_config_register(rspi, 8);
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if (msg->spi->mode &
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(SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
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/* Setup sequencer for messages with multiple transfer modes */
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@ -1267,7 +1264,6 @@ static int rspi_probe(struct platform_device *pdev)
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init_waitqueue_head(&rspi->wait);
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ctlr->bus_num = pdev->id;
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ctlr->setup = rspi_setup;
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ctlr->auto_runtime_pm = true;
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ctlr->transfer_one = ops->transfer_one;
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ctlr->prepare_message = rspi_prepare_message;
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@ -76,7 +76,6 @@
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#define QSPI_PSMAR 0x28
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#define QSPI_PIR 0x2c
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#define QSPI_LPTR 0x30
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#define LPTR_DFT_TIMEOUT 0x10
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#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
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#define STM32_QSPI_MAX_NORCHIP 2
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@ -372,8 +371,7 @@ static int stm32_qspi_setup(struct spi_device *spi)
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flash->presc = presc;
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mutex_lock(&qspi->lock);
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writel_relaxed(LPTR_DFT_TIMEOUT, qspi->io_base + QSPI_LPTR);
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cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_TCEN | CR_SSHIFT | CR_EN;
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cr = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN;
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writel_relaxed(cr, qspi->io_base + QSPI_CR);
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/* set dcr fsize to max address */
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@ -1039,6 +1039,8 @@ static int spi_map_msg(struct spi_controller *ctlr, struct spi_message *msg)
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if (max_tx || max_rx) {
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list_for_each_entry(xfer, &msg->transfers,
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transfer_list) {
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if (!xfer->len)
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continue;
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if (!xfer->tx_buf)
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xfer->tx_buf = ctlr->dummy_tx;
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if (!xfer->rx_buf)
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