redonkable
/
remarkable-linux
1
0
Fork 0
Code Releases Activity

Merge branch 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc 

* 'next/cross-platform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
  ARM: Consolidate the clkdev header files
  ARM: set vga memory base at run-time
  ARM: convert PCI defines to variables
  ARM: pci: make pcibios_assign_all_busses use pci_has_flag
  ARM: remove unnecessary mach/hardware.h includes
  pci: move microblaze and powerpc pci flag functions into asm-generic
  powerpc: rename ppc_pci_*_flags to pci_*_flags

Fix up conflicts in arch/microblaze/include/asm/pci-bridge.h
wifi-calibration
Linus Torvalds 2011-07-26 17:12:10 -07:00
parent 62c9072bee c8f85523e7
commit 3960ef326a
98 changed files with 212 additions and 577 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/Kconfig
View File

@ -242,6 +242,7 @@ config ARCH_INTEGRATOR
select ARM_AMBA
select ARCH_HAS_CPUFREQ
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select ICST
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
@ -253,6 +254,7 @@ config ARCH_REALVIEW
bool "ARM Ltd. RealView family"
select ARM_AMBA
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
@ -268,6 +270,7 @@ config ARCH_VERSATILE
select ARM_AMBA
select ARM_VIC
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
@ -284,6 +287,7 @@ config ARCH_VEXPRESS
select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_PATA_PLATFORM
@ -646,6 +650,7 @@ config ARCH_SHMOBILE
bool "Renesas SH-Mobile / R-Mobile"
select HAVE_CLK
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select GENERIC_CLOCKEVENTS
select NO_IOPORT
select SPARSE_IRQ
@ -825,6 +830,7 @@ config ARCH_U300
select ARM_VIC
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
select HAVE_MACH_CLKDEV
select GENERIC_GPIO
help
Support for ST-Ericsson U300 series mobile platforms.

5
arch/arm/include/asm/clkdev.h
View File

@ -14,7 +14,12 @@
#include <linux/slab.h>
#ifdef CONFIG_HAVE_MACH_CLKDEV
#include <mach/clkdev.h>
#else
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{

12
arch/arm/include/asm/pci.h
View File

@ -3,9 +3,19 @@
#ifdef __KERNEL__
#include <asm-generic/pci-dma-compat.h>
#include <asm-generic/pci-bridge.h>
#include <asm/mach/pci.h> /* for pci_sys_data */
#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
extern unsigned long pcibios_min_io;
#define PCIBIOS_MIN_IO pcibios_min_io
extern unsigned long pcibios_min_mem;
#define PCIBIOS_MIN_MEM pcibios_min_mem
static inline int pcibios_assign_all_busses(void)
{
return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
}
#ifdef CONFIG_PCI_DOMAINS
static inline int pci_domain_nr(struct pci_bus *bus)

5
arch/arm/include/asm/vga.h
View File

@ -2,9 +2,10 @@
#define ASMARM_VGA_H
#include <linux/io.h>
#include <mach/hardware.h>
#define VGA_MAP_MEM(x,s) (PCIMEM_BASE + (x))
extern unsigned long vga_base;
#define VGA_MAP_MEM(x,s) (vga_base + (x))
#define vga_readb(x) (*((volatile unsigned char *)x))
#define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x))

1
arch/arm/lib/ecard.S
View File

@ -12,7 +12,6 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>
#define CPSR2SPSR(rt) \
mrs rt, cpsr; \

1
arch/arm/lib/io-readsw-armv3.S
View File

@ -9,7 +9,6 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>
.Linsw_bad_alignment:
adr r0, .Linsw_bad_align_msg

1
arch/arm/lib/io-writesw-armv3.S
View File

@ -9,7 +9,6 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <mach/hardware.h>
.Loutsw_bad_alignment:
adr r0, .Loutsw_bad_align_msg

7
arch/arm/mach-at91/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

7
arch/arm/mach-bcmring/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

2
arch/arm/mach-bcmring/include/mach/hardware.h
View File

@ -36,8 +36,6 @@
#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
#define RAM_BASE PAGE_OFFSET
#define pcibios_assign_all_busses() 1
/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
#if defined(__KERNEL__)

1
arch/arm/mach-cns3xxx/cns3420vb.c
View File

@ -29,7 +29,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include "core.h"

22
arch/arm/mach-cns3xxx/include/mach/hardware.h
View File

@ -1,22 +0,0 @@
/*
* This file contains the hardware definitions of the Cavium Networks boards.
*
* Copyright 2003 ARM Limited.
* Copyright 2008 Cavium Networks
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License, Version 2, as
* published by the Free Software Foundation.
*/
#ifndef __MACH_HARDWARE_H
#define __MACH_HARDWARE_H
#include <asm/sizes.h>
/* macro to get at IO space when running virtually */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#define pcibios_assign_all_busses() 1
#endif

3
arch/arm/mach-cns3xxx/pcie.c
View File

@ -369,6 +369,9 @@ static int __init cns3xxx_pcie_init(void)
{
int i;
pcibios_min_io = 0;
pcibios_min_mem = 0;
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
"imprecise external abort");

15
arch/arm/mach-davinci/include/mach/clkdev.h
View File

@ -1,15 +0,0 @@
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
struct clk;
static inline int __clk_get(struct clk *clk)
{
return 1;
}
static inline void __clk_put(struct clk *clk)
{
}
#endif

7
arch/arm/mach-dove/include/mach/hardware.h
View File

@ -11,13 +11,6 @@
#include "dove.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE
/* Macros below are required for compatibility with PXA AC'97 driver. */
#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
DOVE_SB_REGS_VIRT_BASE)))

3
arch/arm/mach-dove/pcie.c
View File

@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
@ -228,6 +229,8 @@ static void __init add_pcie_port(int index, unsigned long base)
void __init dove_pcie_init(int init_port0, int init_port1)
{
vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
if (init_port0)
add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);

11
arch/arm/mach-ep93xx/include/mach/clkdev.h
View File

@ -1,11 +0,0 @@
/*
* arch/arm/mach-ep93xx/include/mach/clkdev.h
*/
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

2
arch/arm/mach-ep93xx/include/mach/hardware.h
View File

@ -8,8 +8,6 @@
#include <mach/ep93xx-regs.h>
#include <mach/platform.h>
#define pcibios_assign_all_busses() 0
/*
* The EP93xx has two external crystal oscillators. To generate the
* required high-frequency clocks, the processor uses two phase-locked-

3
arch/arm/mach-footbridge/dc21285.c
View File

@ -295,6 +295,9 @@ void __init dc21285_preinit(void)
unsigned int mem_size, mem_mask;
int cfn_mode;
pcibios_min_mem = 0x81000000;
vga_base = PCIMEM_BASE;
mem_size = (unsigned int)high_memory - PAGE_OFFSET;
for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
if (mem_mask >= mem_size)

5
arch/arm/mach-footbridge/include/mach/hardware.h
View File

@ -100,9 +100,4 @@ extern unsigned int nw_gpio_read(void);
extern void nw_cpld_modify(unsigned int mask, unsigned int set);
#endif
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x81000000
#endif

7
arch/arm/mach-integrator/include/mach/hardware.h
View File

@ -32,13 +32,6 @@
#define IO_SIZE 0x0B000000 // How much?
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
#define PCIMEM_BASE PCI_MEMORY_VADDR
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x6000
#define PCIBIOS_MIN_MEM 0x00100000
/* macro to get at IO space when running virtually */
#ifdef CONFIG_MMU
#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)

5
arch/arm/mach-integrator/pci_v3.c
View File

@ -27,6 +27,7 @@
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <video/vga.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@ -502,6 +503,10 @@ void __init pci_v3_preinit(void)
unsigned int temp;
int ret;
pcibios_min_io = 0x6000;
pcibios_min_mem = 0x00100000;
vga_base = PCI_MEMORY_VADDR;
/*
* Hook in our fault handler for PCI errors
*/

7
arch/arm/mach-iop13xx/include/mach/hardware.h
View File

@ -2,18 +2,11 @@
#define __ASM_ARCH_HARDWARE_H
#include <asm/types.h>
#define pcibios_assign_all_busses() 1
#ifndef __ASSEMBLY__
extern unsigned long iop13xx_pcibios_min_io;
extern unsigned long iop13xx_pcibios_min_mem;
extern u16 iop13xx_dev_id(void);
extern void iop13xx_set_atu_mmr_bases(void);
#endif
#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
/*
* Generic chipset bits
*

5
arch/arm/mach-iop13xx/pci.c
View File

@ -39,8 +39,6 @@ u32 iop13xx_atue_mem_base;
u32 iop13xx_atux_mem_base;
size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size;
unsigned long iop13xx_pcibios_min_io = 0;
unsigned long iop13xx_pcibios_min_mem = 0;
EXPORT_SYMBOL(iop13xx_atue_mem_base);
EXPORT_SYMBOL(iop13xx_atux_mem_base);
@ -971,7 +969,8 @@ void __init iop13xx_pci_init(void)
__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
/* Setup the Min Address for PCI memory... */
iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
pcibios_min_io = 0;
pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
/* if Linux is given control of an ATU
* clear out its prior configuration,

3
arch/arm/mach-iop32x/include/mach/hardware.h
View File

@ -18,9 +18,6 @@
* but when we read them, we convert them to virtual addresses. See
* arch/arm/plat-iop/pci.c.
*/
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__
void iop32x_init_irq(void);

3
arch/arm/mach-iop33x/include/mach/hardware.h
View File

@ -18,9 +18,6 @@
* but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop3xx/iop3xx-pci.c
*/
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__
void iop33x_init_irq(void);

8
arch/arm/mach-ixp2000/include/mach/hardware.h
View File

@ -19,16 +19,8 @@
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
/*
* This needs to be platform-specific?
*/
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
#include "ixp2000-regs.h" /* Chipset Registers */
#define pcibios_assign_all_busses() 0
/*
* Platform helper functions
*/

5
arch/arm/mach-ixp2000/pci.c
View File

@ -196,6 +196,11 @@ clear_master_aborts(void)
void __init
ixp2000_pci_preinit(void)
{
pci_set_flags(0);
pcibios_min_io = 0;
pcibios_min_mem = 0;
#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
/*
* Configure the PCI unit to properly byteswap I/O transactions,

4
arch/arm/mach-ixp23xx/include/mach/hardware.h
View File

@ -15,13 +15,9 @@
#define __ASM_ARCH_HARDWARE_H
/* PCI IO info */
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0xe0000000
#include "ixp23xx.h"
#define pcibios_assign_all_busses() 0
/*
* Platform helper functions
*/

5
arch/arm/mach-ixp23xx/pci.c
View File

@ -227,6 +227,11 @@ static void __init ixp23xx_pci_common_init(void)
void __init ixp23xx_pci_preinit(void)
{
pcibios_min_io = 0;
pcibios_min_mem = 0xe0000000;
pci_set_flags(0);
ixp23xx_pci_common_init();
hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,

5
arch/arm/mach-ixp4xx/common-pci.c
View File

@ -346,6 +346,11 @@ void __init ixp4xx_pci_preinit(void)
{
unsigned long cpuid = read_cpuid_id();
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
#else
pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
#endif
/*
* Determine which PCI read method to use.
* Rev 0 IXP425 requires workaround.

5
arch/arm/mach-ixp4xx/include/mach/hardware.h
View File

@ -17,19 +17,14 @@
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
#define PCIBIOS_MIN_IO 0x00001000
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4FFFFFFF
#else
#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4BFFFFFF
#endif
#define ARCH_HAS_DMA_SET_COHERENT_MASK
#define pcibios_assign_all_busses() 1
/* Register locations and bits */
#include "ixp4xx-regs.h"

7
arch/arm/mach-kirkwood/include/mach/hardware.h
View File

@ -11,11 +11,4 @@
#include "kirkwood.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
#endif

3
arch/arm/mach-kirkwood/pcie.c
View File

@ -12,6 +12,7 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
@ -271,6 +272,8 @@ static void __init add_pcie_port(int index, unsigned long base)
void __init kirkwood_pcie_init(unsigned int portmask)
{
vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
if (portmask & KW_PCIE0)
add_pcie_port(0, PCIE_VIRT_BASE);

9
arch/arm/mach-ks8695/include/mach/hardware.h
View File

@ -42,13 +42,4 @@
#define KS8695_PCIIO_PA 0x80000000
#define KS8695_PCIIO_SIZE SZ_64K
/*
* PCI support
*/
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0
#endif

3
arch/arm/mach-ks8695/pci.c
View File

@ -317,6 +317,9 @@ void __init ks8695_init_pci(struct ks8695_pci_cfg *cfg)
return;
}
pcibios_min_io = 0;
pcibios_min_mem = 0;
printk(KERN_INFO "PCI: Initialising\n");
ks8695_show_pciregs();

25
arch/arm/mach-lpc32xx/include/mach/clkdev.h
View File

@ -1,25 +0,0 @@
/*
* arch/arm/mach-lpc32xx/include/mach/clkdev.h
*
* Author: Kevin Wells <kevin.wells@nxp.com>
*
* Copyright (C) 2010 NXP Semiconductors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_CLKDEV_H
#define __ASM_ARCH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

7
arch/arm/mach-mmp/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif /* __ASM_MACH_CLKDEV_H */

19
arch/arm/mach-msm/include/mach/clkdev.h
View File

@ -1,19 +0,0 @@
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ASM_ARCH_MSM_CLKDEV_H
#define __ASM_ARCH_MSM_CLKDEV_H
struct clk;
static inline int __clk_get(struct clk *clk) { return 1; }
static inline void __clk_put(struct clk *clk) { }
#endif

7
arch/arm/mach-mv78xx0/include/mach/hardware.h
View File

@ -11,11 +11,4 @@
#include "mv78xx0.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
#endif

3
arch/arm/mach-mv78xx0/pcie.c
View File

@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
@ -297,6 +298,8 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
void __init mv78xx0_pcie_init(int init_port0, int init_port1)
{
vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
if (init_port0) {
add_pcie_port(0, 0, PCIE00_VIRT_BASE);
if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {

7
arch/arm/mach-mxs/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __MACH_MXS_CLKDEV_H__
#define __MACH_MXS_CLKDEV_H__
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

7
arch/arm/mach-nomadik/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

7
arch/arm/mach-nuc93x/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

5
arch/arm/mach-omap1/include/mach/clkdev.h
View File

@ -1,5 +0,0 @@
/*
* arch/arm/mach-omap1/include/mach/clkdev.h
*/
#include <plat/clkdev.h>

5
arch/arm/mach-omap2/include/mach/clkdev.h
View File

@ -1,5 +0,0 @@
/*
* arch/arm/mach-omap2/include/mach/clkdev.h
*/
#include <plat/clkdev.h>

7
arch/arm/mach-orion5x/include/mach/hardware.h
View File

@ -11,11 +11,4 @@
#include "orion5x.h"
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00001000
#define PCIBIOS_MIN_MEM 0x01000000
#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE
#endif

2
arch/arm/mach-orion5x/pci.c
View File

@ -560,6 +560,8 @@ int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
if (nr == 0) {
orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
ret = pcie_setup(sys);

7
arch/arm/mach-pnx4008/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

3
arch/arm/mach-pxa/cm-x2xx-pci.c
View File

@ -125,6 +125,9 @@ static void cmx2xx_pci_preinit(void)
{
pr_info("Initializing CM-X2XX PCI subsystem\n");
pcibios_min_io = 0;
pcibios_min_mem = 0;
__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
pr_info("PCI Bridge found.\n");

7
arch/arm/mach-pxa/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

3
arch/arm/mach-pxa/include/mach/hardware.h
View File

@ -337,9 +337,6 @@ extern unsigned long get_clock_tick_rate(void);
#endif
#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0
#define pcibios_assign_all_busses() 1
#define ARCH_HAS_DMA_SET_COHERENT_MASK
#endif

8
arch/arm/mach-sa1100/include/mach/hardware.h
View File

@ -76,12 +76,4 @@ static inline unsigned long get_clock_tick_rate(void)
#include "SA-1101.h"
#endif
#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
#define PCIBIOS_MIN_IO 0
#define PCIBIOS_MIN_MEM 0
#define pcibios_assign_all_busses() 1
#define HAVE_ARCH_PCI_SET_DMA_MASK 1
#endif
#endif /* _ASM_ARCH_HARDWARE_H */

3
arch/arm/mach-sa1100/pci-nanoengine.c
View File

@ -252,6 +252,9 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
pcibios_min_io = 0;
pcibios_min_mem = 0;
if (nr == 0) {
sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
sys->io_offset = 0x400;

6
arch/arm/mach-shark/include/mach/hardware.h
View File

@ -12,11 +12,5 @@
#define UNCACHEABLE_ADDR 0xdf010000
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x6000
#define PCIBIOS_MIN_MEM 0x50000000
#define PCIMEM_BASE 0xe8000000
#endif

12
arch/arm/mach-shark/pci.c
View File

@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
@ -37,8 +38,15 @@ static struct hw_pci shark_pci __initdata = {
static int __init shark_pci_init(void)
{
if (machine_is_shark())
pci_common_init(&shark_pci);
if (!machine_is_shark())
return;
pcibios_min_io = 0x6000;
pcibios_min_mem = 0x50000000;
vga_base = 0xe8000000;
pci_common_init(&shark_pci);
return 0;
}

19
arch/arm/mach-spear3xx/include/mach/clkdev.h
View File

@ -1,19 +0,0 @@
/*
* arch/arm/mach-spear3xx/include/mach/clkdev.h
*
* Clock Dev framework definitions for SPEAr3xx machine family
*
* Copyright (C) 2009 ST Microelectronics
* Viresh Kumar<viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
#include <plat/clkdev.h>
#endif /* __MACH_CLKDEV_H */

19
arch/arm/mach-spear6xx/include/mach/clkdev.h
View File

@ -1,19 +0,0 @@
/*
* arch/arm/mach-spear6xx/include/mach/clkdev.h
*
* Clock Dev framework definitions for SPEAr6xx machine family
*
* Copyright (C) 2009 ST Microelectronics
* Viresh Kumar<viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
#include <plat/clkdev.h>
#endif /* __MACH_CLKDEV_H */

34
arch/arm/mach-tegra/include/mach/clkdev.h
View File

@ -1,34 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/clkdev.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
struct clk;
static inline int __clk_get(struct clk *clk)
{
return 1;
}
static inline void __clk_put(struct clk *clk)
{
}
#endif

28
arch/arm/mach-tegra/include/mach/hardware.h
View File

@ -1,28 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/hardware.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:
* Colin Cross <ccross@google.com>
* Erik Gilling <konkers@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_HARDWARE_H
#define __MACH_TEGRA_HARDWARE_H
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0
#define pcibios_assign_all_busses() 1
#endif

1
arch/arm/mach-tegra/include/mach/system.h
View File

@ -21,7 +21,6 @@
#ifndef __MACH_TEGRA_SYSTEM_H
#define __MACH_TEGRA_SYSTEM_H
#include <mach/hardware.h>
#include <mach/iomap.h>
extern void (*arch_reset)(char mode, const char *cmd);

1
arch/arm/mach-tegra/io.c
View File

@ -24,7 +24,6 @@
#include <linux/mm.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/page.h>
#include <asm/mach/map.h>

2
arch/arm/mach-tegra/pcie.c
View File

@ -912,6 +912,8 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
if (!(init_port0 || init_port1))
return -ENODEV;
pcibios_min_mem = 0;
err = tegra_pcie_get_resources();
if (err)
return err;

1
arch/arm/mach-tegra/platsmp.c
View File

@ -21,7 +21,6 @@
#include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>

7
arch/arm/mach-ux500/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

6
arch/arm/mach-versatile/include/mach/hardware.h
View File

@ -30,12 +30,6 @@
#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
/* CIK guesswork */
#define PCIBIOS_MIN_IO 0x44000000
#define PCIBIOS_MIN_MEM 0x50000000
#define pcibios_assign_all_busses() 1
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)

3
arch/arm/mach-versatile/pci.c
View File

@ -311,6 +311,9 @@ struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
void __init pci_versatile_preinit(void)
{
pcibios_min_io = 0x44000000;
pcibios_min_mem = 0x50000000;
__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);

7
arch/arm/mach-w90x900/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

12
arch/arm/mm/iomap.c
View File

@ -9,6 +9,9 @@
#include <linux/ioport.h>
#include <linux/io.h>
unsigned long vga_base;
EXPORT_SYMBOL(vga_base);
#ifdef __io
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
@ -23,6 +26,15 @@ EXPORT_SYMBOL(ioport_unmap);
#endif
#ifdef CONFIG_PCI
unsigned long pcibios_min_io = 0x1000;
EXPORT_SYMBOL(pcibios_min_io);
unsigned long pcibios_min_mem = 0x01000000;
EXPORT_SYMBOL(pcibios_min_mem);
unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
EXPORT_SYMBOL(pci_flags);
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
resource_size_t start = pci_resource_start(dev, bar);

1
arch/arm/mm/proc-xsc3.S
View File

@ -28,7 +28,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>

3
arch/arm/plat-iop/pci.c
View File

@ -374,6 +374,9 @@ void __init iop3xx_pci_preinit_cond(void)
void __init iop3xx_pci_preinit(void)
{
pcibios_min_io = 0;
pcibios_min_mem = 0;
iop3xx_atu_disable();
iop3xx_atu_setup();
iop3xx_atu_debug();

7
arch/arm/plat-mxc/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

13
arch/arm/plat-omap/include/plat/clkdev.h
View File

@ -1,13 +0,0 @@
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
static inline int __clk_get(struct clk *clk)
{
return 1;
}
static inline void __clk_put(struct clk *clk)
{
}
#endif

20
arch/arm/plat-spear/include/plat/clkdev.h
View File

@ -1,20 +0,0 @@
/*
* arch/arm/plat-spear/include/plat/clkdev.h
*
* Clock Dev framework definitions for SPEAr platform
*
* Copyright (C) 2009 ST Microelectronics
* Viresh Kumar<viresh.kumar@st.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __PLAT_CLKDEV_H
#define __PLAT_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif /* __PLAT_CLKDEV_H */

7
arch/arm/plat-tcc/include/mach/clkdev.h
View File

@ -1,7 +0,0 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

64
arch/microblaze/include/asm/pci-bridge.h
View File

@ -10,28 +10,19 @@
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <asm-generic/pci-bridge.h>
struct device_node;
enum {
/* Force re-assigning all resources (ignore firmware
* setup completely)
*/
PCI_REASSIGN_ALL_RSRC = 0x00000001,
/* Do not try to assign, just use existing setup */
PCI_PROBE_ONLY = 0x00000004,
/* Don't bother with ISA alignment unless the bridge has
* ISA forwarding enabled
*/
PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
/* Enable domain numbers in /proc */
PCI_ENABLE_PROC_DOMAINS = 0x00000010,
/* ... except for domain 0 */
PCI_COMPAT_DOMAIN_0 = 0x00000020,
};
#ifdef CONFIG_PCI
extern struct list_head hose_list;
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
return 0;
}
#endif
/*
* Structure of a PCI controller (host bridge)
@ -151,40 +142,5 @@ extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
extern void pcibios_free_controller(struct pci_controller *phb);
extern void pcibios_setup_phb_resources(struct pci_controller *hose);
#ifdef CONFIG_PCI
extern unsigned int pci_flags;
static inline void pci_set_flags(int flags)
{
pci_flags = flags;
}
static inline void pci_add_flags(int flags)
{
pci_flags |= flags;
}
static inline int pci_has_flag(int flag)
{
return pci_flags & flag;
}
extern struct list_head hose_list;
extern int pcibios_vaddr_is_ioport(void __iomem *address);
#else
static inline int pcibios_vaddr_is_ioport(void __iomem *address)
{
return 0;
}
static inline void pci_set_flags(int flags) { }
static inline void pci_add_flags(int flags) { }
static inline int pci_has_flag(int flag)
{
return 0;
}
#endif /* CONFIG_PCI */
#endif /* __KERNEL__ */
#endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */

50
arch/powerpc/include/asm/pci-bridge.h
View File

@ -10,58 +10,10 @@
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <asm-generic/pci-bridge.h>
struct device_node;
enum {
/* Force re-assigning all resources (ignore firmware
* setup completely)
*/
PPC_PCI_REASSIGN_ALL_RSRC = 0x00000001,
/* Re-assign all bus numbers */
PPC_PCI_REASSIGN_ALL_BUS = 0x00000002,
/* Do not try to assign, just use existing setup */
PPC_PCI_PROBE_ONLY = 0x00000004,
/* Don't bother with ISA alignment unless the bridge has
* ISA forwarding enabled
*/
PPC_PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
/* Enable domain numbers in /proc */
PPC_PCI_ENABLE_PROC_DOMAINS = 0x00000010,
/* ... except for domain 0 */
PPC_PCI_COMPAT_DOMAIN_0 = 0x00000020,
};
#ifdef CONFIG_PCI
extern unsigned int ppc_pci_flags;
static inline void ppc_pci_set_flags(int flags)
{
ppc_pci_flags = flags;
}
static inline void ppc_pci_add_flags(int flags)
{
ppc_pci_flags |= flags;
}
static inline int ppc_pci_has_flag(int flag)
{
return (ppc_pci_flags & flag);
}
#else
static inline void ppc_pci_set_flags(int flags) { }
static inline void ppc_pci_add_flags(int flags) { }
static inline int ppc_pci_has_flag(int flag)
{
return 0;
}
#endif
/*
* Structure of a PCI controller (host bridge)
*/

2
arch/powerpc/include/asm/pci.h
View File

@ -44,7 +44,7 @@ struct pci_dev;
* bus numbers (don't do that on ppc64 yet !)
*/
#define pcibios_assign_all_busses() \
(ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS))
(pci_has_flag(PCI_REASSIGN_ALL_BUS))
static inline void pcibios_set_master(struct pci_dev *dev)
{

22
arch/powerpc/kernel/pci-common.c
View File

@ -50,7 +50,7 @@ static int global_phb_number; /* Global phb counter */
resource_size_t isa_mem_base;
/* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
unsigned int ppc_pci_flags = 0;
unsigned int pci_flags = 0;
static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
@ -842,9 +842,9 @@ int pci_proc_domain(struct pci_bus *bus)
{
struct pci_controller *hose = pci_bus_to_host(bus);
if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
return 0;
if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
return hose->global_number != 0;
return 1;
}
@ -920,13 +920,13 @@ static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
struct resource *res = dev->resource + i;
if (!res->flags)
continue;
/* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
/* On platforms that have PCI_PROBE_ONLY set, we don't
* consider 0 as an unassigned BAR value. It's technically
* a valid value, but linux doesn't like it... so when we can
* re-assign things, we do so, but if we can't, we keep it
* around and hope for the best...
*/
if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
if (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY)) {
pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
pci_name(dev), i,
(unsigned long long)res->start,
@ -973,7 +973,7 @@ static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
int i;
/* We don't do anything if PCI_PROBE_ONLY is set */
if (ppc_pci_flags & PPC_PCI_PROBE_ONLY)
if (pci_has_flag(PCI_PROBE_ONLY))
return 0;
/* Job is a bit different between memory and IO */
@ -1143,7 +1143,7 @@ void __devinit pci_fixup_cardbus(struct pci_bus *bus)
static int skip_isa_ioresource_align(struct pci_dev *dev)
{
if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
return 1;
return 0;
@ -1271,7 +1271,7 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
* and as such ensure proper re-allocation
* later.
*/
if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
if (pci_has_flag(PCI_REASSIGN_ALL_RSRC))
goto clear_resource;
pr = pci_find_parent_resource(bus->self, res);
if (pr == res) {
@ -1456,7 +1456,7 @@ void __init pcibios_resource_survey(void)
list_for_each_entry(b, &pci_root_buses, node)
pcibios_allocate_bus_resources(b);
if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
pcibios_allocate_resources(0);
pcibios_allocate_resources(1);
}
@ -1465,7 +1465,7 @@ void __init pcibios_resource_survey(void)
* the low IO area and the VGA memory area if they intersect the
* bus available resources to avoid allocating things on top of them
*/
if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
if (!pci_has_flag(PCI_PROBE_ONLY)) {
list_for_each_entry(b, &pci_root_buses, node)
pcibios_reserve_legacy_regions(b);
}
@ -1473,7 +1473,7 @@ void __init pcibios_resource_survey(void)
/* Now, if the platform didn't decide to blindly trust the firmware,
* we proceed to assigning things that were left unassigned
*/
if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
if (!pci_has_flag(PCI_PROBE_ONLY)) {
pr_debug("PCI: Assigning unassigned resources...\n");
pci_assign_unassigned_resources();
}

2
arch/powerpc/kernel/pci_32.c
View File

@ -230,7 +230,7 @@ static int __init pcibios_init(void)
printk(KERN_INFO "PCI: Probing PCI hardware\n");
if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS)
if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
pci_assign_all_buses = 1;
/* Scan all of the recorded PCI controllers. */

4
arch/powerpc/kernel/pci_64.c
View File

@ -55,12 +55,12 @@ static int __init pcibios_init(void)
ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
if (pci_probe_only)
ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
pci_add_flags(PCI_PROBE_ONLY);
/* On ppc64, we always enable PCI domains and we keep domain 0
* backward compatible in /proc for video cards
*/
ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
/* Scan all of the recorded PCI controllers. */
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {

2
arch/powerpc/kernel/rtas_pci.c
View File

@ -291,7 +291,7 @@ void __init find_and_init_phbs(void)
prop = of_get_property(of_chosen,
"linux,pci-assign-all-buses", NULL);
if (prop && *prop)
ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS;
pci_add_flags(PCI_REASSIGN_ALL_BUS);
#endif /* CONFIG_PPC32 */
}
}

2
arch/powerpc/platforms/40x/ep405.c
View File

@ -100,7 +100,7 @@ static void __init ep405_setup_arch(void)
/* Find & init the BCSR CPLD */
ep405_init_bcsr();
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
}
static int __init ep405_probe(void)

2
arch/powerpc/platforms/40x/ppc40x_simple.c
View File

@ -61,7 +61,7 @@ static const char *board[] __initdata = {
static int __init ppc40x_probe(void)
{
if (of_flat_dt_match(of_get_flat_dt_root(), board)) {
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
return 1;
}

2
arch/powerpc/platforms/40x/walnut.c
View File

@ -51,7 +51,7 @@ static int __init walnut_probe(void)
if (!of_flat_dt_is_compatible(root, "ibm,walnut"))
return 0;
ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC;
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
return 1;
}

2
arch/powerpc/platforms/44x/canyonlands.c
View File

@ -55,7 +55,7 @@ static int __init ppc460ex_probe(void)
{
unsigned long root = of_get_flat_dt_root();
if (of_flat_dt_is_compatible(root, "amcc,canyonlands")) {
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
return 1;
}
return 0;

2
arch/powerpc/platforms/44x/ebony.c
View File

@ -54,7 +54,7 @@ static int __init ebony_probe(void)
if (!of_flat_dt_is_compatible(root, "ibm,ebony"))
return 0;
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
return 1;
}

2
arch/powerpc/platforms/44x/ppc44x_simple.c
View File

@ -72,7 +72,7 @@ static int __init ppc44x_probe(void)
for (i = 0; i < ARRAY_SIZE(board); i++) {
if (of_flat_dt_is_compatible(root, board[i])) {
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
return 1;
}
}

2
arch/powerpc/platforms/44x/sam440ep.c
View File

@ -51,7 +51,7 @@ static int __init sam440ep_probe(void)
if (!of_flat_dt_is_compatible(root, "acube,sam440ep"))
return 0;
ppc_pci_set_flags(PPC_PCI_REASSIGN_ALL_RSRC);
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
return 1;
}

2
arch/powerpc/platforms/52xx/mpc52xx_pci.c
View File

@ -371,7 +371,7 @@ mpc52xx_add_bridge(struct device_node *node)
pr_debug("Adding MPC52xx PCI host bridge %s\n", node->full_name);
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
if (of_address_to_resource(node, 0, &rsrc) != 0) {
printk(KERN_ERR "Can't get %s resources\n", node->full_name);

2
arch/powerpc/platforms/82xx/pq2.c
View File

@ -53,7 +53,7 @@ static void __init pq2_pci_add_bridge(struct device_node *np)
if (of_address_to_resource(np, 0, &r) || r.end - r.start < 0x10b)
goto err;
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
hose = pcibios_alloc_controller(np);
if (!hose)

2
arch/powerpc/platforms/chrp/pci.c
View File

@ -199,7 +199,7 @@ static void __init setup_peg2(struct pci_controller *hose, struct device_node *d
printk ("RTAS supporting Pegasos OF not found, please upgrade"
" your firmware\n");
}
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
/* keep the reference to the root node */
}

6
arch/powerpc/platforms/powermac/pci.c
View File

@ -732,7 +732,7 @@ static void __init setup_bandit(struct pci_controller *hose,
static int __init setup_uninorth(struct pci_controller *hose,
struct resource *addr)
{
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
has_uninorth = 1;
hose->ops = &macrisc_pci_ops;
hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
@ -998,7 +998,7 @@ void __init pmac_pci_init(void)
struct device_node *np, *root;
struct device_node *ht = NULL;
ppc_pci_set_flags(PPC_PCI_CAN_SKIP_ISA_ALIGN);
pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
root = of_find_node_by_path("/");
if (root == NULL) {
@ -1057,7 +1057,7 @@ void __init pmac_pci_init(void)
* some offset between bus number and domains for now when we
* assign all busses should help for now
*/
if (ppc_pci_has_flag(PPC_PCI_REASSIGN_ALL_BUS))
if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
pcibios_assign_bus_offset = 0x10;
#endif
}

4
arch/powerpc/sysdev/fsl_pci.c
View File

@ -351,7 +351,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
printk(KERN_WARNING "Can't get bus-range for %s, assume"
" bus 0\n", dev->full_name);
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;
@ -640,7 +640,7 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
" bus 0\n", dev->full_name);
}
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
hose = pcibios_alloc_controller(dev);
if (!hose)
return -ENOMEM;

2
arch/powerpc/sysdev/grackle.c
View File

@ -57,7 +57,7 @@ void __init setup_grackle(struct pci_controller *hose)
{
setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
if (of_machine_is_compatible("PowerMac1,1"))
ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
pci_add_flags(PCI_REASSIGN_ALL_BUS);
if (of_machine_is_compatible("AAPL,PowerBook1998"))
grackle_set_loop_snoop(hose, 1);
#if 0 /* Disabled for now, HW problems ??? */

2
arch/powerpc/sysdev/ppc4xx_pci.c
View File

@ -1977,7 +1977,7 @@ static int __init ppc4xx_pci_find_bridges(void)
{
struct device_node *np;
ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
#ifdef CONFIG_PPC4xx_PCI_EXPRESS
for_each_compatible_node(np, NULL, "ibm,plb-pciex")

3
drivers/clk/Kconfig
View File

@ -2,3 +2,6 @@
config CLKDEV_LOOKUP
bool
select HAVE_CLK
config HAVE_MACH_CLKDEV
bool

62
include/asm-generic/pci-bridge.h 100644
View File

@ -0,0 +1,62 @@
/*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_GENERIC_PCI_BRIDGE_H
#define _ASM_GENERIC_PCI_BRIDGE_H
#ifdef __KERNEL__
enum {
/* Force re-assigning all resources (ignore firmware
* setup completely)
*/
PCI_REASSIGN_ALL_RSRC = 0x00000001,
/* Re-assign all bus numbers */
PCI_REASSIGN_ALL_BUS = 0x00000002,
/* Do not try to assign, just use existing setup */
PCI_PROBE_ONLY = 0x00000004,
/* Don't bother with ISA alignment unless the bridge has
* ISA forwarding enabled
*/
PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
/* Enable domain numbers in /proc */
PCI_ENABLE_PROC_DOMAINS = 0x00000010,
/* ... except for domain 0 */
PCI_COMPAT_DOMAIN_0 = 0x00000020,
};
#ifdef CONFIG_PCI
extern unsigned int pci_flags;
static inline void pci_set_flags(int flags)
{
pci_flags = flags;
}
static inline void pci_add_flags(int flags)
{
pci_flags |= flags;
}
static inline int pci_has_flag(int flag)
{
return pci_flags & flag;
}
#else
static inline void pci_set_flags(int flags) { }
static inline void pci_add_flags(int flags) { }
static inline int pci_has_flag(int flag)
{
return 0;
}
#endif /* CONFIG_PCI */
#endif /* __KERNEL__ */
#endif /* _ASM_GENERIC_PCI_BRIDGE_H */