[POWERPC] pasemi: UART udbg support
Early debug output for PA Semi UART. Uses the 2.05 CI real mode ops. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -185,6 +185,13 @@ config PPC_EARLY_DEBUG_ISERIES
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Select this to enable early debugging for legacy iSeries. You need
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to hit "Ctrl-x Ctrl-x" to see the messages on the console.
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config PPC_EARLY_DEBUG_PAS_REALMODE
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bool "PA Semi real mode"
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depends on PPC_PASEMI
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help
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Select this to enable early debugging for PA Semi.
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Output will be on UART0.
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config PPC_EARLY_DEBUG_BEAT
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bool "Beat HV Console"
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depends on PPC_CELLEB
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@ -311,6 +311,46 @@ _GLOBAL(real_writeb)
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blr
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#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
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#ifdef CONFIG_PPC_PASEMI
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/* No support in all binutils for these yet, so use defines */
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#define LBZCIX(RT,RA,RB) .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))
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#define STBCIX(RS,RA,RB) .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
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_GLOBAL(real_205_readb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsrd r0
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sync
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isync
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LBZCIX(r3,0,r3)
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isync
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mtmsrd r7
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sync
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isync
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blr
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_GLOBAL(real_205_writeb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsrd r0
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sync
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isync
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STBCIX(r3,0,r4)
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isync
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mtmsrd r7
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sync
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isync
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blr
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#endif /* CONFIG_PPC_PASEMI */
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#ifdef CONFIG_CPU_FREQ_PMAC64
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/*
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* SCOM access functions for 970 (FX only for now)
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@ -47,6 +47,8 @@ void __init udbg_early_init(void)
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udbg_init_iseries();
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#elif defined(CONFIG_PPC_EARLY_DEBUG_BEAT)
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udbg_init_debug_beat();
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#elif defined(CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE)
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udbg_init_pas_realmode();
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#endif
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}
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@ -14,6 +14,8 @@
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extern u8 real_readb(volatile u8 __iomem *addr);
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extern void real_writeb(u8 data, volatile u8 __iomem *addr);
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extern u8 real_205_readb(volatile u8 __iomem *addr);
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extern void real_205_writeb(u8 data, volatile u8 __iomem *addr);
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struct NS16550 {
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/* this struct must be packed */
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@ -167,3 +169,25 @@ void __init udbg_init_maple_realmode(void)
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udbg_getc_poll = NULL;
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}
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#endif /* CONFIG_PPC_MAPLE */
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#ifdef CONFIG_PPC_PASEMI
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void udbg_pas_real_putc(char c)
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{
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if (udbg_comport) {
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while ((real_205_readb(&udbg_comport->lsr) & LSR_THRE) == 0)
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/* wait for idle */;
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real_205_writeb(c, &udbg_comport->thr); eieio();
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if (c == '\n')
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udbg_pas_real_putc('\r');
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}
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}
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void udbg_init_pas_realmode(void)
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{
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udbg_comport = (volatile struct NS16550 __iomem *)0xfcff03f8;
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udbg_putc = udbg_pas_real_putc;
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udbg_getc = NULL;
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udbg_getc_poll = NULL;
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}
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#endif /* CONFIG_PPC_MAPLE */
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@ -41,6 +41,7 @@ extern void __init udbg_early_init(void);
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extern void __init udbg_init_debug_lpar(void);
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extern void __init udbg_init_pmac_realmode(void);
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extern void __init udbg_init_maple_realmode(void);
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extern void __init udbg_init_pas_realmode(void);
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extern void __init udbg_init_iseries(void);
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extern void __init udbg_init_rtas_panel(void);
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extern void __init udbg_init_rtas_console(void);
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