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ath5k: update AR5K_PHY_RESTART_DIV_GC values to match masks 

#define AR5K_PHY_RESTART_DIV_GC               0x001c0000
is 3 bit wide.

The previous values of 0xc and 0x8 are 4bit wide and bigger than the mask.

Writing 0 and 1 to AR5K_PHY_RESTART_DIV_GC is consistent with the comments and
initvals we have in the HAL.

Signed-off-by: Bruno Randolf <br1@einfach.org>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
wifi-calibration
Bruno Randolf 2010-06-07 13:11:25 +09:00 committed by John W. Linville
parent 84efa0e7aa
commit 39d5b2c83c
1 changed files with 2 additions and 2 deletions
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4
drivers/net/wireless/ath/ath5k/phy.c
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@ -1768,13 +1768,13 @@ ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
if (enable) {
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
AR5K_PHY_RESTART_DIV_GC, 0xc);
AR5K_PHY_RESTART_DIV_GC, 1);
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
AR5K_PHY_FAST_ANT_DIV_EN);
} else {
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
AR5K_PHY_RESTART_DIV_GC, 0x8);
AR5K_PHY_RESTART_DIV_GC, 0);
AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
AR5K_PHY_FAST_ANT_DIV_EN);