sh: Revert lazy dcache writeback changes.
These ended up causing too many problems on older parts, revert for now.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
c87a711134
commit
39e688a94b
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@ -156,8 +156,6 @@ void r7780rp_insw(unsigned long port, void *dst, unsigned long count)
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while (count--)
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*buf++ = *p;
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flush_dcache_all();
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}
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void r7780rp_insl(unsigned long port, void *dst, unsigned long count)
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@ -204,8 +202,6 @@ void r7780rp_outsw(unsigned long port, const void *src, unsigned long count)
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while (count--)
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*p = *buf++;
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flush_dcache_all();
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}
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void r7780rp_outsl(unsigned long port, const void *src, unsigned long count)
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@ -14,7 +14,6 @@
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#include <linux/module.h>
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#include <linux/io.h>
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#include <asm/machvec.h>
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#include <asm/cacheflush.h>
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#ifdef CONFIG_CPU_SH3
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/* SH3 has a PCMCIA bug that needs a dummy read from area 6 for a
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@ -96,7 +95,6 @@ void generic_insw(unsigned long port, void *dst, unsigned long count)
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while (count--)
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*buf++ = *port_addr;
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flush_dcache_all();
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dummy_read();
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}
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@ -171,7 +169,6 @@ void generic_outsw(unsigned long port, const void *src, unsigned long count)
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while (count--)
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*port_addr = *buf++;
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flush_dcache_all();
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dummy_read();
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}
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@ -237,20 +237,10 @@ static inline void flush_cache_4096(unsigned long start,
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/*
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* Write back & invalidate the D-cache of the page.
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* (To avoid "alias" issues)
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*
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* This uses a lazy write-back on UP, which is explicitly
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* disabled on SMP.
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*/
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void flush_dcache_page(struct page *page)
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{
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#ifndef CONFIG_SMP
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struct address_space *mapping = page_mapping(page);
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if (mapping && !mapping_mapped(mapping))
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set_bit(PG_dcache_dirty, &page->flags);
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else
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#endif
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{
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if (test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = PHYSADDR(page_address(page));
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unsigned long addr = CACHE_OC_ADDRESS_ARRAY;
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int i, n;
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@ -3,11 +3,11 @@
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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* Copyright (C) 2004 Alex Song
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/mman.h>
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@ -51,6 +51,7 @@ static inline void cache_wback_all(void)
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if ((data & v) == v)
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ctrl_outl(data & ~v, addr);
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}
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addrstart += current_cpu_data.dcache.way_incr;
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@ -127,11 +128,7 @@ static void __flush_dcache_page(unsigned long phys)
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*/
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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if (mapping && !mapping_mapped(mapping))
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set_bit(PG_dcache_dirty, &page->flags);
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else
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if (test_bit(PG_mapped, &page->flags))
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__flush_dcache_page(PHYSADDR(page_address(page)));
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}
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@ -23,6 +23,7 @@ extern struct mutex p3map_mutex[];
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*/
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void clear_user_page(void *to, unsigned long address, struct page *page)
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{
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__set_bit(PG_mapped, &page->flags);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0)
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clear_page(to);
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else {
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@ -58,6 +59,7 @@ void clear_user_page(void *to, unsigned long address, struct page *page)
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void copy_user_page(void *to, void *from, unsigned long address,
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struct page *page)
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{
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__set_bit(PG_mapped, &page->flags);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0)
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copy_page(to, from);
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else {
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@ -82,3 +84,23 @@ void copy_user_page(void *to, void *from, unsigned long address,
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mutex_unlock(&p3map_mutex[(address & CACHE_ALIAS)>>12]);
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}
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}
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/*
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* For SH-4, we have our own implementation for ptep_get_and_clear
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*/
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inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_t pte = *ptep;
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pte_clear(mm, addr, ptep);
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if (!pte_not_present(pte)) {
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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struct page *page = pfn_to_page(pfn);
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struct address_space *mapping = page_mapping(page);
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if (!mapping || !mapping_writably_mapped(mapping))
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__clear_bit(PG_mapped, &page->flags);
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}
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}
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return pte;
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}
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@ -7,7 +7,9 @@
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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@ -74,6 +76,7 @@ void clear_user_page(void *to, unsigned long address, struct page *pg)
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{
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struct page *page = virt_to_page(to);
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__set_bit(PG_mapped, &page->flags);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
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clear_page(to);
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__flush_wback_region(to, PAGE_SIZE);
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@ -92,11 +95,12 @@ void clear_user_page(void *to, unsigned long address, struct page *pg)
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* @from: P1 address
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* @address: U0 address to be mapped
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*/
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void copy_user_page(void *to, void *from, unsigned long address,
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struct page *pg)
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void copy_user_page(void *to, void *from, unsigned long address, struct page *pg)
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{
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struct page *page = virt_to_page(to);
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__set_bit(PG_mapped, &page->flags);
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if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
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copy_page(to, from);
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__flush_wback_region(to, PAGE_SIZE);
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__flush_wback_region(to, PAGE_SIZE);
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}
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}
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/*
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* For SH7705, we have our own implementation for ptep_get_and_clear
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* Copied from pg-sh4.c
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*/
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inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_t pte = *ptep;
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pte_clear(mm, addr, ptep);
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if (!pte_not_present(pte)) {
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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struct page *page = pfn_to_page(pfn);
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struct address_space *mapping = page_mapping(page);
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if (!mapping || !mapping_writably_mapped(mapping))
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__clear_bit(PG_mapped, &page->flags);
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}
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}
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return pte;
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}
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@ -2,17 +2,15 @@
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* TLB flushing operations for SH with an MMU.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 - 2006 Paul Mundt
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/mm.h>
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#include <linux/io.h>
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#include <asm/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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@ -140,54 +138,3 @@ void local_flush_tlb_all(void)
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ctrl_barrier();
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local_irq_restore(flags);
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}
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void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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unsigned long pteval;
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unsigned long vpn;
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struct page *page;
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unsigned long pfn = pte_pfn(pte);
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struct address_space *mapping;
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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mapping = page_mapping(page);
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if (mapping) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
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if (dirty)
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__flush_wback_region((void *)P1SEGADDR(phys),
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PAGE_SIZE);
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}
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = (address & MMU_VPN_MASK) | get_asid();
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ctrl_outl(vpn, MMU_PTEH);
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pteval = pte_val(pte);
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#ifdef CONFIG_CPU_HAS_PTEA
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/* Set PTEA register */
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/* TODO: make this look less hacky */
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ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
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#endif
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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#if defined(CONFIG_SH_WRITETHROUGH) && defined(CONFIG_CPU_SH4)
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pteval |= _PAGE_WT;
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#endif
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/* conveniently, we want all the software flags to be 0 anyway */
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ctrl_outl(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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@ -8,9 +8,69 @@
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/io.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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unsigned long pteval;
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unsigned long vpn;
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/* Ptrace may call this routine. */
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if (vma && current->active_mm != vma->vm_mm)
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return;
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#if defined(CONFIG_SH7705_CACHE_32KB)
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{
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struct page *page = pte_page(pte);
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unsigned long pfn = pte_pfn(pte);
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if (pfn_valid(pfn) && !test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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__flush_wback_region((void *)P1SEGADDR(phys),
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PAGE_SIZE);
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__set_bit(PG_mapped, &page->flags);
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}
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}
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#endif
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = (address & MMU_VPN_MASK) | get_asid();
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ctrl_outl(vpn, MMU_PTEH);
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pteval = pte_val(pte);
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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/* conveniently, we want all the software flags to be 0 anyway */
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ctrl_outl(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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void local_flush_tlb_one(unsigned long asid, unsigned long page)
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{
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for (i = 0; i < ways; i++)
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ctrl_outl(data, addr + (i << 8));
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}
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@ -8,9 +8,74 @@
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*
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* Released under the terms of the GNU GPL v2.0.
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*/
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#include <linux/io.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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void update_mmu_cache(struct vm_area_struct * vma,
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unsigned long address, pte_t pte)
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{
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unsigned long flags;
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unsigned long pteval;
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unsigned long vpn;
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struct page *page;
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unsigned long pfn;
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/* Ptrace may call this routine. */
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if (vma && current->active_mm != vma->vm_mm)
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return;
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pfn = pte_pfn(pte);
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if (pfn_valid(pfn)) {
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page = pfn_to_page(pfn);
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if (!test_bit(PG_mapped, &page->flags)) {
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unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
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__flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE);
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__set_bit(PG_mapped, &page->flags);
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}
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}
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local_irq_save(flags);
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/* Set PTEH register */
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vpn = (address & MMU_VPN_MASK) | get_asid();
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ctrl_outl(vpn, MMU_PTEH);
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pteval = pte_val(pte);
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/* Set PTEA register */
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if (cpu_data->flags & CPU_HAS_PTEA)
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/* TODO: make this look less hacky */
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ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA);
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/* Set PTEL register */
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pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
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#ifdef CONFIG_SH_WRITETHROUGH
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pteval |= _PAGE_WT;
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#endif
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/* conveniently, we want all the software flags to be 0 anyway */
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ctrl_outl(pteval, MMU_PTEL);
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/* Load the TLB */
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asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
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local_irq_restore(flags);
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}
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void local_flush_tlb_one(unsigned long asid, unsigned long page)
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{
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@ -28,3 +93,4 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
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ctrl_outl(data, addr);
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back_to_P1();
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}
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@ -30,8 +30,5 @@ extern void __flush_invalidate_region(void *start, int size);
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#define HAVE_ARCH_UNMAPPED_AREA
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/* Page flag for lazy dcache write-back for the aliasing UP caches */
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#define PG_dcache_dirty PG_arch_1
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_CACHEFLUSH_H */
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@ -36,6 +36,8 @@
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/* 32KB cache, 4kb PAGE sizes need to check bit 12 */
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#define CACHE_ALIAS 0x00001000
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#define PG_mapped PG_arch_1
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void flush_cache_all(void);
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void flush_cache_mm(struct mm_struct *mm);
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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@ -39,4 +39,6 @@ void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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/* Initialization of P3 area for copy_user_page */
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void p3_cache_init(void);
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#define PG_mapped PG_arch_1
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#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
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@ -583,6 +583,11 @@ struct mm_struct;
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extern unsigned int kobjsize(const void *objp);
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#endif /* !CONFIG_MMU */
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#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
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#endif
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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||||
extern void paging_init(void);
|
||||
|
||||
|
|
Loading…
Reference in a new issue