clk: stm32mp1: add Debug clocks
RCC manages clock for debug and trace. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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@ -260,6 +260,10 @@ static const char * const mco2_src[] = {
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"ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
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};
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static const char * const ck_trace_src[] = {
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"ck_axi"
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};
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static const struct clk_div_table axi_div_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
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{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
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@ -280,6 +284,12 @@ static const struct clk_div_table apb_div_table[] = {
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{ 0 },
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};
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static const struct clk_div_table ck_trace_div_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
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{ 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
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{ 0 },
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};
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#define MAX_MUX_CLK 2
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struct stm32_mmux {
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@ -1980,6 +1990,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
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_GATE(RCC_MCO2CFGR, 12, 0),
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_MUX(RCC_MCO2CFGR, 0, 3, 0),
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_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
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/* Debug clocks */
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FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
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GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
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GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
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COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
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_GATE(RCC_DBGCFGR, 9, 0),
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_NO_MUX,
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_DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
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};
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struct stm32_clock_match_data {
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