net: dsa: mv88e6xxx: rework Switch MAC setter
Switches such as 88E6185 as 3 Switch MAC registers in Global 1. Newer chips such as 88E6352 have freed these registers in favor of an indirect access in a Switch MAC/WoL/WoF register in Global 2. Explicit this difference with G1 and G2 helpers and flags. Also, note that this indirect access is a single-register which doesn't require to wait for the operation to complete (like Switch MAC, Trunk Mapping, etc.), in contrary to multi-registers indirect accesses with several operations and a busy bit. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -283,68 +283,6 @@ static int mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
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return ret;
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}
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static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
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{
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struct mv88e6xxx_chip *chip = ds_to_priv(ds);
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int err;
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err = mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
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(addr[0] << 8) | addr[1]);
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if (err)
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return err;
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err = mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
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(addr[2] << 8) | addr[3]);
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if (err)
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return err;
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return mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
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(addr[4] << 8) | addr[5]);
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}
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static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
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{
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struct mv88e6xxx_chip *chip = ds_to_priv(ds);
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int ret;
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int i;
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for (i = 0; i < 6; i++) {
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int j;
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/* Write the MAC address byte. */
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ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
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GLOBAL2_SWITCH_MAC_BUSY |
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(i << 8) | addr[i]);
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if (ret)
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return ret;
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/* Wait for the write to complete. */
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for (j = 0; j < 16; j++) {
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ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2,
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GLOBAL2_SWITCH_MAC);
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if (ret < 0)
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return ret;
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if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
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break;
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}
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if (j == 16)
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
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{
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struct mv88e6xxx_chip *chip = ds_to_priv(ds);
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SWITCH_MAC))
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return mv88e6xxx_set_addr_indirect(ds, addr);
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else
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return mv88e6xxx_set_addr_direct(ds, addr);
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}
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static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
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int addr, int regnum)
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{
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@ -3019,6 +2957,24 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
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return 0;
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}
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static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
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{
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int err;
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err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
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(addr[0] << 8) | addr[1]);
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if (err)
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return err;
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err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
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(addr[2] << 8) | addr[3]);
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if (err)
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return err;
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return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
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(addr[4] << 8) | addr[5]);
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}
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static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
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{
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struct dsa_switch *ds = chip->ds;
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@ -3194,6 +3150,28 @@ static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
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return 0;
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}
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/* Indirect write to the Switch MAC/WoL/WoF register */
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static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
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unsigned int pointer, u8 data)
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{
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u16 val = (pointer << 8) | data;
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return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
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}
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static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
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{
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int i, err;
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for (i = 0; i < 6; i++) {
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err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
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if (err)
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break;
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}
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return err;
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}
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static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
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{
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u16 reg;
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@ -3327,6 +3305,24 @@ unlock:
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return err;
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}
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static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
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{
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struct mv88e6xxx_chip *chip = ds_to_priv(ds);
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int err;
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mutex_lock(&chip->reg_lock);
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/* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
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if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
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err = mv88e6xxx_g2_set_switch_mac(chip, addr);
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else
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err = mv88e6xxx_g1_set_switch_mac(chip, addr);
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mutex_unlock(&chip->reg_lock);
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return err;
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}
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static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
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int reg)
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{
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@ -303,7 +303,6 @@
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#define GLOBAL2_PVT_ADDR 0x0b
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#define GLOBAL2_PVT_DATA 0x0c
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#define GLOBAL2_SWITCH_MAC 0x0d
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#define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
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#define GLOBAL2_ATU_STATS 0x0e
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#define GLOBAL2_PRIO_OVERRIDE 0x0f
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#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
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@ -390,6 +389,7 @@ enum mv88e6xxx_cap {
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MV88E6XXX_CAP_GLOBAL2,
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MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
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MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
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MV88E6XXX_CAP_G2_SWITCH_MAC, /* (0x0d) Switch MAC/WoL/WoF */
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/* Multi-chip Addressing Mode.
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* Some chips require an indirect SMI access when their SMI device
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@ -415,13 +415,6 @@ enum mv88e6xxx_cap {
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*/
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MV88E6XXX_CAP_STU,
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/* Switch MAC/WoL/WoF register.
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* This requires an indirect access to set the switch MAC address
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* through GLOBAL2_SWITCH_MAC, otherwise GLOBAL_MAC_01, GLOBAL_MAC_23,
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* and GLOBAL_MAC_45 are used with a direct access.
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*/
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MV88E6XXX_CAP_SWITCH_MAC_WOL_WOF,
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/* Internal temperature sensor.
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* Available from any enabled port's PHY register 26, page 6.
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*/
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@ -440,12 +433,12 @@ enum mv88e6xxx_cap {
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#define MV88E6XXX_FLAG_GLOBAL2 BIT(MV88E6XXX_CAP_GLOBAL2)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT(MV88E6XXX_CAP_G2_MGMT_EN_2X)
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#define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT(MV88E6XXX_CAP_G2_MGMT_EN_0X)
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#define MV88E6XXX_FLAG_G2_SWITCH_MAC BIT(MV88E6XXX_CAP_G2_SWITCH_MAC)
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#define MV88E6XXX_FLAG_MULTI_CHIP BIT(MV88E6XXX_CAP_MULTI_CHIP)
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#define MV88E6XXX_FLAG_PPU BIT(MV88E6XXX_CAP_PPU)
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#define MV88E6XXX_FLAG_PPU_ACTIVE BIT(MV88E6XXX_CAP_PPU_ACTIVE)
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#define MV88E6XXX_FLAG_SMI_PHY BIT(MV88E6XXX_CAP_SMI_PHY)
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#define MV88E6XXX_FLAG_STU BIT(MV88E6XXX_CAP_STU)
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#define MV88E6XXX_FLAG_SWITCH_MAC BIT(MV88E6XXX_CAP_SWITCH_MAC_WOL_WOF)
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#define MV88E6XXX_FLAG_TEMP BIT(MV88E6XXX_CAP_TEMP)
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#define MV88E6XXX_FLAG_TEMP_LIMIT BIT(MV88E6XXX_CAP_TEMP_LIMIT)
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#define MV88E6XXX_FLAG_VTU BIT(MV88E6XXX_CAP_VTU)
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@ -470,9 +463,9 @@ enum mv88e6xxx_cap {
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_SWITCH_MAC | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_SWITCH_MAC | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_VTU)
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@ -489,10 +482,10 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_SWITCH_MAC | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_SMI_PHY | \
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MV88E6XXX_FLAG_SWITCH_MAC | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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MV88E6XXX_FLAG_VTU)
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@ -501,11 +494,11 @@ enum mv88e6xxx_cap {
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(MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_SWITCH_MAC | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_SMI_PHY | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_SWITCH_MAC | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_VTU)
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@ -515,11 +508,11 @@ enum mv88e6xxx_cap {
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MV88E6XXX_FLAG_GLOBAL2 | \
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MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
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MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
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MV88E6XXX_FLAG_G2_SWITCH_MAC | \
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MV88E6XXX_FLAG_MULTI_CHIP | \
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MV88E6XXX_FLAG_PPU_ACTIVE | \
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MV88E6XXX_FLAG_SMI_PHY | \
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MV88E6XXX_FLAG_STU | \
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MV88E6XXX_FLAG_SWITCH_MAC | \
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MV88E6XXX_FLAG_TEMP | \
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MV88E6XXX_FLAG_TEMP_LIMIT | \
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MV88E6XXX_FLAG_VTU)
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