cxgb4: avoid disabling FEC by default
Recent Chelsio firmware started using few port capablity bits to manage FEC and as driver was not aware of FEC changes those bits were zeroed, consequently disabling FEC. Avoid zeroing those bits and default to whatever the firmware tells us the Link is currently advertising. Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -108,6 +108,12 @@ enum {
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PAUSE_AUTONEG = 1 << 2
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};
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enum {
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FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
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FEC_RS = 1 << 1, /* Reed-Solomon */
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FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
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};
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struct port_stats {
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u64 tx_octets; /* total # of octets in good frames */
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u64 tx_frames; /* all good frames */
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@ -432,6 +438,9 @@ struct link_config {
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unsigned int speed; /* actual link speed */
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unsigned char requested_fc; /* flow control user has requested */
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unsigned char fc; /* actual link flow control */
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unsigned char auto_fec; /* Forward Error Correction: */
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unsigned char requested_fec; /* "automatic" (IEEE 802.3), */
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unsigned char fec; /* requested, and actual in use */
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unsigned char autoneg; /* autonegotiating? */
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unsigned char link_ok; /* link up? */
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unsigned char link_down_rc; /* link down reason */
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@ -3707,7 +3707,8 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
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struct link_config *lc)
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{
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struct fw_port_cmd c;
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unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
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unsigned int mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
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unsigned int fc = 0, fec = 0, fw_fec = 0;
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lc->link_ok = 0;
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if (lc->requested_fc & PAUSE_RX)
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@ -3715,6 +3716,13 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
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if (lc->requested_fc & PAUSE_TX)
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fc |= FW_PORT_CAP_FC_TX;
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fec = lc->requested_fec & FEC_AUTO ? lc->auto_fec : lc->requested_fec;
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if (fec & FEC_RS)
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fw_fec |= FW_PORT_CAP_FEC_RS;
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if (fec & FEC_BASER_RS)
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fw_fec |= FW_PORT_CAP_FEC_BASER_RS;
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memset(&c, 0, sizeof(c));
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c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
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FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
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@ -3725,13 +3733,15 @@ int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
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if (!(lc->supported & FW_PORT_CAP_ANEG)) {
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c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
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fc);
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fc | fw_fec);
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lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
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} else if (lc->autoneg == AUTONEG_DISABLE) {
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c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
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c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc |
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fw_fec | mdi);
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lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
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} else
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c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
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c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc |
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fw_fec | mdi);
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return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
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}
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@ -7407,13 +7417,26 @@ static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
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* Initializes the SW state maintained for each link, including the link's
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* capabilities and default speed/flow-control/autonegotiation settings.
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*/
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static void init_link_config(struct link_config *lc, unsigned int caps)
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static void init_link_config(struct link_config *lc, unsigned int pcaps,
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unsigned int acaps)
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{
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lc->supported = caps;
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lc->supported = pcaps;
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lc->lp_advertising = 0;
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lc->requested_speed = 0;
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lc->speed = 0;
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lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
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lc->auto_fec = 0;
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/* For Forward Error Control, we default to whatever the Firmware
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* tells us the Link is currently advertising.
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*/
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if (acaps & FW_PORT_CAP_FEC_RS)
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lc->auto_fec |= FEC_RS;
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if (acaps & FW_PORT_CAP_FEC_BASER_RS)
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lc->auto_fec |= FEC_BASER_RS;
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lc->requested_fec = FEC_AUTO;
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lc->fec = lc->auto_fec;
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if (lc->supported & FW_PORT_CAP_ANEG) {
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lc->advertising = lc->supported & ADVERT_MASK;
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lc->autoneg = AUTONEG_ENABLE;
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@ -7991,7 +8014,8 @@ int t4_init_portinfo(struct port_info *pi, int mbox,
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pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
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pi->mod_type = FW_PORT_MOD_TYPE_NA;
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init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
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init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap),
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be16_to_cpu(c.u.info.acap));
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return 0;
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}
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@ -2263,9 +2263,9 @@ enum fw_port_cap {
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FW_PORT_CAP_ANEG = 0x0100,
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FW_PORT_CAP_MDIX = 0x0200,
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FW_PORT_CAP_MDIAUTO = 0x0400,
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FW_PORT_CAP_FEC = 0x0800,
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FW_PORT_CAP_TECHKR = 0x1000,
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FW_PORT_CAP_TECHKX4 = 0x2000,
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FW_PORT_CAP_FEC_RS = 0x0800,
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FW_PORT_CAP_FEC_BASER_RS = 0x1000,
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FW_PORT_CAP_FEC_RESERVED = 0x2000,
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FW_PORT_CAP_802_3_PAUSE = 0x4000,
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FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
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};
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