scsi: hisi_sas: Add v2 hw support for different refclk
The hip06 D03 and hip07 D05 boards have different reference clock frequencies for the SAS controller. Register PHY_CTRL needs to be programmed differently according to this frequency, so add support for this. The default register setting in PHY_CTRL is for 50MHz, so only update this register when the refclk frequency is 66MHz. For ACPI we expect the _RST handler to set the correct value for PHY_CTRL (we're forced to take different approach for DT and ACPI as ACPI does not support fixed-clock device). Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -13,6 +13,7 @@
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#define _HISI_SAS_H_
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/dmapool.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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@ -183,6 +184,7 @@ struct hisi_hba {
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u32 ctrl_reset_reg;
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u32 ctrl_reset_sts_reg;
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u32 ctrl_clock_ena_reg;
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u32 refclk_frequency_mhz;
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u8 sas_addr[SAS_ADDR_SIZE];
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int n_phy;
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@ -1396,6 +1396,7 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
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struct hisi_hba *hisi_hba;
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struct device *dev = &pdev->dev;
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struct device_node *np = pdev->dev.of_node;
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struct clk *refclk;
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shost = scsi_host_alloc(&hisi_sas_sht, sizeof(*hisi_hba));
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if (!shost)
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@ -1432,6 +1433,12 @@ static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
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goto err_out;
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}
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refclk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(refclk))
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dev_info(dev, "no ref clk property\n");
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else
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hisi_hba->refclk_frequency_mhz = clk_get_rate(refclk) / 1000000;
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if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy))
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goto err_out;
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@ -836,7 +836,9 @@ static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
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hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
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hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
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hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
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hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
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if (hisi_hba->refclk_frequency_mhz == 66)
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hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
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/* else, do nothing -> leave it how you found it */
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}
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for (i = 0; i < hisi_hba->queue_count; i++) {
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