ARM: ux500: move UART pin control to the device tree
This moves the static, device-tied pin control configuration out of the board file board-mop500-pins.c and into the device tree. We create a new .dtsi-file to be shared between all the MOP500-related boards, that include all HREF variants and the Snowball board. Assign pin states for HREF and Snowball boards alike. Cc: Lee Jones <lee.jones@linaro.org> Cc: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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114
arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
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114
arch/arm/boot/dts/ste-href-family-pinctrl.dtsi
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@ -0,0 +1,114 @@
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/*
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* Copyright 2013 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "ste-nomadik-pinctrl.dtsi"
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/ {
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soc {
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pinctrl {
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/* Settings for all UART default and sleep states */
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uart0 {
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uart0_default_mode: uart0_default {
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default_mux {
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ste,function = "u0";
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ste,pins = "u0_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
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ste,config = <&out_hi>;
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};
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};
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uart0_sleep_mode: uart0_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO1_AJ3"; /* RTS */
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ste,config = <&slpm_out_hi_wkup_pdis>;
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};
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sleep_cfg3 {
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ste,pins = "GPIO3_AH3"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart1 {
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uart1_default_mode: uart1_default {
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default_mux {
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ste,function = "u1";
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ste,pins = "u1rxtx_a_1";
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};
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default_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart1_sleep_mode: uart1_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO4_AH6"; /* RXD */
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ste,config = <&slpm_in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO5_AG6"; /* TXD */
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ste,config = <&slpm_out_wkup_pdis>;
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};
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};
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};
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uart2 {
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uart2_default_mode: uart2_default {
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default_mux {
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ste,function = "u2";
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ste,pins = "u2rxtx_c_1";
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};
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default_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_pu>;
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};
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default_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_hi>;
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};
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};
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uart2_sleep_mode: uart2_sleep {
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sleep_cfg1 {
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ste,pins = "GPIO29_W2"; /* RXD */
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ste,config = <&in_wkup_pdis>;
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};
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sleep_cfg2 {
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ste,pins = "GPIO30_W3"; /* TXD */
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ste,config = <&out_wkup_pdis>;
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};
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};
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};
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};
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};
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};
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@ -11,6 +11,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "ste-dbx5x0.dtsi"
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#include "ste-dbx5x0.dtsi"
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#include "ste-href-family-pinctrl.dtsi"
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/ {
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/ {
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memory {
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memory {
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@ -30,14 +31,23 @@
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soc {
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soc {
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uart@80120000 {
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uart@80120000 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart0_default_mode>;
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pinctrl-1 = <&uart0_sleep_mode>;
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status = "okay";
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status = "okay";
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};
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};
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uart@80121000 {
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uart@80121000 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart1_default_mode>;
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pinctrl-1 = <&uart1_sleep_mode>;
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status = "okay";
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status = "okay";
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};
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};
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uart@80007000 {
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uart@80007000 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart2_default_mode>;
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pinctrl-1 = <&uart2_sleep_mode>;
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status = "okay";
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status = "okay";
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};
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};
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@ -11,6 +11,7 @@
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/dts-v1/;
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/dts-v1/;
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#include "ste-dbx5x0.dtsi"
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#include "ste-dbx5x0.dtsi"
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#include "ste-href-family-pinctrl.dtsi"
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/ {
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/ {
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model = "Calao Systems Snowball platform with device tree";
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model = "Calao Systems Snowball platform with device tree";
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@ -155,14 +156,23 @@
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};
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};
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uart@80120000 {
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uart@80120000 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart0_default_mode>;
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pinctrl-1 = <&uart0_sleep_mode>;
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status = "okay";
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status = "okay";
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};
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};
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uart@80121000 {
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uart@80121000 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart1_default_mode>;
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pinctrl-1 = <&uart1_sleep_mode>;
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status = "okay";
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status = "okay";
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};
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};
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uart@80007000 {
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uart@80007000 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&uart2_default_mode>;
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pinctrl-1 = <&uart2_sleep_mode>;
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status = "okay";
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status = "okay";
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};
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};
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@ -65,16 +65,12 @@ BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|
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PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
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PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
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BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
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BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
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PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
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PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
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BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|
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PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
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BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
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BIAS(out_lo_wkup_pdis, PIN_SLPM_OUTPUT_LOW|
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PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
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PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
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BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
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BIAS(in_wkup_pdis_en, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
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PIN_SLPM_PDIS_ENABLED);
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PIN_SLPM_PDIS_ENABLED);
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BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
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BIAS(in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|
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PIN_SLPM_PDIS_DISABLED);
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PIN_SLPM_PDIS_DISABLED);
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BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
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PIN_SLPM_PDIS_DISABLED);
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/* We use these to define hog settings that are always done on boot */
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/* We use these to define hog settings that are always done on boot */
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#define DB8500_MUX_HOG(group,func) \
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#define DB8500_MUX_HOG(group,func) \
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@ -375,51 +371,11 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
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* TODO: set for snowball and HREF really??
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* TODO: set for snowball and HREF really??
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*/
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*/
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DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
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DB8500_PIN_HOG("GPIO218_AH11", gpio_in_pu),
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/*
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* UART0, we do not mux in u0 here.
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* uart-0 pins gpio configuration should be kept intact to prevent
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* a glitch in tx line when the tty dev is opened. Later these pins
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* are configured by uart driver
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*/
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DB8500_PIN_HOG("GPIO0_AJ5", in_pu), /* CTS */
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DB8500_PIN_HOG("GPIO1_AJ3", out_hi), /* RTS */
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DB8500_PIN_HOG("GPIO2_AH4", in_pu), /* RXD */
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DB8500_PIN_HOG("GPIO3_AH3", out_hi), /* TXD */
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/*
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* Mux in UART2 on altfunction C and set pull-ups.
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* TODO: is this used on U8500 variants and Snowball really?
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* The setting on GPIO31 conflicts with magnetometer use on hrefv60
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*/
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/* default state for UART2 */
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DB8500_MUX("u2rxtx_c_1", "u2", "uart2"),
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DB8500_PIN("GPIO29_W2", in_pu, "uart2"), /* RXD */
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DB8500_PIN("GPIO30_W3", out_hi, "uart2"), /* TXD */
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/* Sleep state for UART2 */
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DB8500_PIN_SLEEP("GPIO29_W2", in_wkup_pdis, "uart2"),
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DB8500_PIN_SLEEP("GPIO30_W3", out_wkup_pdis, "uart2"),
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/*
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/*
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* The following pin sets were known as "runtime pins" before being
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* The following pin sets were known as "runtime pins" before being
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* converted to the pinctrl model. Here we model them as "default"
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* converted to the pinctrl model. Here we model them as "default"
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* states.
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* states.
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*/
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*/
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/* Mux in UART0 after initialization */
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DB8500_MUX("u0_a_1", "u0", "uart0"),
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DB8500_PIN("GPIO0_AJ5", in_pu, "uart0"), /* CTS */
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DB8500_PIN("GPIO1_AJ3", out_hi, "uart0"), /* RTS */
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DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
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DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
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/* Sleep state for UART0 */
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DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
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DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
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DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
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DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
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/* Mux in UART1 after initialization */
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DB8500_MUX("u1rxtx_a_1", "u1", "uart1"),
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DB8500_PIN("GPIO4_AH6", in_pu, "uart1"), /* RXD */
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DB8500_PIN("GPIO5_AG6", out_hi, "uart1"), /* TXD */
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/* Sleep state for UART1 */
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DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
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DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
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/* MSP1 for ALSA codec */
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/* MSP1 for ALSA codec */
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DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
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DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
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DB8500_MUX_HOG("msp1_a_1", "msp1"),
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DB8500_MUX_HOG("msp1_a_1", "msp1"),
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@ -822,10 +778,6 @@ static struct pinctrl_map __initdata mop500_pinmap[] = {
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DB8500_PIN_HOG("GPIO7_AG5", in_pu),
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DB8500_PIN_HOG("GPIO7_AG5", in_pu),
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/* TC35892 IRQ, pull up the line, let the driver mux in the pin */
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/* TC35892 IRQ, pull up the line, let the driver mux in the pin */
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DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
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DB8500_PIN_HOG("GPIO217_AH12", gpio_in_pu),
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/* Mux in UART1 and set the pull-ups */
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DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
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DB8500_PIN_HOG("GPIO4_AH6", in_pu), /* RXD */
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DB8500_PIN_HOG("GPIO5_AG6", out_hi), /* TXD */
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/*
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/*
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* Runtime stuff: make it possible to mux in the SKE keypad
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* Runtime stuff: make it possible to mux in the SKE keypad
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* and bias the pins
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* and bias the pins
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@ -971,10 +923,6 @@ static struct pinctrl_map __initdata hrefv60_pinmap[] = {
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};
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};
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static struct pinctrl_map __initdata u9500_pinmap[] = {
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static struct pinctrl_map __initdata u9500_pinmap[] = {
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/* Mux in UART1 (just RX/TX) and set the pull-ups */
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DB8500_MUX_HOG("u1rxtx_a_1", "u1"),
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DB8500_PIN_HOG("GPIO4_AH6", in_pu),
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DB8500_PIN_HOG("GPIO5_AG6", out_hi),
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/* WLAN_IRQ line */
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/* WLAN_IRQ line */
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DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
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DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
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/* HSI */
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/* HSI */
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