ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init
This patch postpone MPU activation till __after_proc_init (which is placed in .text section) rather than doing it in __setup_mpu. It allows us ignore used-only-once .head.text section while programming PMSAv8 MPU (for PMSAv7 it stays covered anyway). Tested-by: Szemz? András <sza@esh.hu> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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@ -125,11 +125,24 @@ __secondary_data:
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*/
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.text
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__after_proc_init:
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#ifdef CONFIG_ARM_MPU
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M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB)
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M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB)
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M_CLASS(ldr r3, [r12, 0x50])
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AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0
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and r3, r3, #(MMFR0_PMSA) @ PMSA field
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teq r3, #(MMFR0_PMSAv7) @ PMSA v7
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#endif
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#ifdef CONFIG_CPU_CP15
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/*
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* CP15 system control register value returned in r0 from
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* the CPU init function.
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*/
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#ifdef CONFIG_ARM_MPU
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biceq r0, r0, #CR_BR @ Disable the 'default mem-map'
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orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on)
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#endif
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#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
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orr r0, r0, #CR_A
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#else
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@ -145,7 +158,15 @@ __after_proc_init:
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bic r0, r0, #CR_I
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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isb
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#elif defined (CONFIG_CPU_V7M)
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#ifdef CONFIG_ARM_MPU
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ldreq r3, [r12, MPU_CTRL]
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biceq r3, #MPU_CTRL_PRIVDEFENA
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orreq r3, #MPU_CTRL_ENABLE
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streq r3, [r12, MPU_CTRL]
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isb
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#endif
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/* For V7M systems we want to modify the CCR similarly to the SCTLR */
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #V7M_SCB_CCR_DC
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@ -156,9 +177,7 @@ __after_proc_init:
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #V7M_SCB_CCR_IC
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#endif
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movw r3, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
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movt r3, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)
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str r0, [r3]
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str r0, [r12, V7M_SCB_CCR]
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#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */
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ret lr
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ENDPROC(__after_proc_init)
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@ -282,19 +301,6 @@ M_CLASS(ldr r0, [r12, #MPU_TYPE])
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setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
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3: isb
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#endif
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/* Enable the MPU */
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AR_CLASS(mrc p15, 0, r0, c1, c0, 0) @ Read SCTLR
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AR_CLASS(bic r0, r0, #CR_BR) @ Disable the 'default mem-map'
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AR_CLASS(orr r0, r0, #CR_M) @ Set SCTRL.M (MPU on)
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AR_CLASS(mcr p15, 0, r0, c1, c0, 0) @ Enable MPU
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M_CLASS(ldr r0, [r12, #MPU_CTRL])
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M_CLASS(bic r0, #MPU_CTRL_PRIVDEFENA)
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M_CLASS(orr r0, #MPU_CTRL_ENABLE)
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M_CLASS(str r0, [r12, #MPU_CTRL])
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isb
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ret lr
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ENDPROC(__setup_pmsa_v7)
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@ -352,13 +358,6 @@ ENTRY(__secondary_setup_pmsa_v7)
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cmp r4, #0
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bgt 1b
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/* Enable the MPU */
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mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
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bic r0, r0, #CR_BR @ Disable the 'default mem-map'
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orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
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mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
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isb
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ret lr
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ENDPROC(__secondary_setup_pmsa_v7)
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