ARM: exynos: Remove static mapping of SCU SFR
Lets remove static mapping of SCU SFR mainly used in CORTEX-A9 SoC based boards. Instead use mapping from device tree node of SCU. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> [mszyprow: rebased, added fallback to scu_a9_get_base() when no SCU DT node is available, removed compatibility break warning, fixed non-SMP build, keep SCU base mapping to avoid issues with calls from CPUidle] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -141,6 +141,11 @@ extern void exynos_cpu_restore_register(void);
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extern void exynos_pm_central_suspend(void);
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extern int exynos_pm_central_resume(void);
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extern void exynos_enter_aftr(void);
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#ifdef CONFIG_SMP
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extern void exynos_scu_enable(void);
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#else
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static inline void exynos_scu_enable(void) { }
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#endif
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extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
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@ -24,15 +24,6 @@
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#include "common.h"
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
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.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
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.length = SZ_8K,
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.type = MT_DEVICE,
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},
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};
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static struct platform_device exynos_cpuidle = {
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.name = "exynos_cpuidle",
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#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
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@ -85,17 +76,6 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
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return 1;
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}
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/*
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* exynos_map_io
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*
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* register the standard cpu IO areas
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*/
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static void __init exynos_map_io(void)
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{
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if (soc_is_exynos4())
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iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
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}
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static void __init exynos_init_io(void)
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{
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debug_ll_io_init();
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@ -104,8 +84,6 @@ static void __init exynos_init_io(void)
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/* detect cpu id and rev. */
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s5p_init_cpu(S5P_VA_CHIPID);
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exynos_map_io();
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}
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/*
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@ -15,6 +15,4 @@
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#define EXYNOS_PA_CHIPID 0x10000000
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#define EXYNOS4_PA_COREPERI 0x10500000
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#endif /* __ASM_ARCH_MAP_H */
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@ -163,6 +163,26 @@ int exynos_cluster_power_state(int cluster)
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S5P_CORE_LOCAL_PWR_EN);
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}
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/**
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* exynos_scu_enable : enables SCU for Cortex-A9 based system
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*/
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void exynos_scu_enable(void)
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{
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struct device_node *np;
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static void __iomem *scu_base;
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if (!scu_base) {
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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of_node_put(np);
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} else {
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scu_base = ioremap(scu_a9_get_base(), SZ_4K);
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}
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}
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scu_enable(scu_base);
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}
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static void __iomem *cpu_boot_reg_base(void)
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{
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if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
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@ -219,11 +239,6 @@ static void write_pen_release(int val)
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sync_cache_w(&pen_release);
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}
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)(S5P_VA_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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static void exynos_secondary_init(unsigned int cpu)
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@ -389,7 +404,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
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exynos_set_delayed_reset_assertion(true);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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scu_enable(scu_base_addr());
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exynos_scu_enable();
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/*
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* Write the address of secondary startup into the
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@ -22,8 +22,6 @@
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#include <asm/suspend.h>
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#include <asm/cacheflush.h>
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#include <mach/map.h>
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#include "common.h"
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static inline void __iomem *exynos_boot_vector_addr(void)
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@ -172,7 +170,7 @@ void exynos_enter_aftr(void)
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cpu_suspend(0, exynos_aftr_finisher);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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scu_enable(S5P_VA_SCU);
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exynos_scu_enable();
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if (call_firmware_op(resume) == -ENOSYS)
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exynos_cpu_restore_register();
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}
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@ -30,8 +30,6 @@
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <mach/map.h>
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#include <plat/pm-common.h>
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#include "common.h"
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@ -401,7 +399,7 @@ static void exynos_pm_resume(void)
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goto early_wakeup;
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if (cpuid == ARM_CPU_PART_CORTEX_A9)
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scu_enable(S5P_VA_SCU);
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exynos_scu_enable();
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if (call_firmware_op(resume) == -ENOSYS
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&& cpuid == ARM_CPU_PART_CORTEX_A9)
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@ -11,10 +11,6 @@
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#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
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#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
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#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
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#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
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#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
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#define VA_VIC0 VA_VIC(0)
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#define VA_VIC1 VA_VIC(1)
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