staging: tidspbridge: set3 remove hungarian from structs
hungarian notation will be removed from the elements inside structures, the next varibles will be renamed: Original: Replacement: dw_seg_base_va seg_base_va dw_self_loop self_loop dw_state state dw_tc_endianism tc_endianism dw_test_base test_base dw_type type dw_val1 val1 dw_val2 val2 dw_val3 val3 dw_va va dw_virt_base virt_base dw_vm_base vm_base dw_vm_size vm_size pfn_allocate allocate pfn_brd_mem_copy brd_mem_copy pfn_brd_mem_map brd_mem_map pfn_brd_mem_un_map brd_mem_un_map pfn_brd_mem_write brd_mem_write pfn_brd_monitor brd_monitor pfn_brd_read brd_read Signed-off-by: Rene Sapiens <rene.sapiens@ti.com> Signed-off-by: Omar Ramirez Luna <omar.ramirez@ti.com>
This commit is contained in:
parent
5108de0ae0
commit
3c882de542
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@ -332,9 +332,9 @@ struct bridge_dev_context {
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u32 dsp_clk_m2_base; /* DSP Clock Module m2 */
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u32 public_rhea; /* Pub Rhea */
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u32 int_addr; /* MB INTR reg */
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u32 dw_tc_endianism; /* TC Endianism register */
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u32 dw_test_base; /* DSP MMU Mapped registers */
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u32 dw_self_loop; /* Pointer to the selfloop */
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u32 tc_endianism; /* TC Endianism register */
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u32 test_base; /* DSP MMU Mapped registers */
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u32 self_loop; /* Pointer to the selfloop */
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u32 dsp_start_add; /* API Boot vector */
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u32 internal_size; /* Internal memory size */
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@ -115,7 +115,7 @@ int bridge_chnl_add_io_req(struct chnl_object *chnl_obj, void *host_buf,
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* Check the channel state: only queue chirp if channel state
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* allows it.
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*/
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dw_state = pchnl->dw_state;
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dw_state = pchnl->state;
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if (dw_state != CHNL_STATEREADY) {
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if (dw_state & CHNL_STATECANCEL)
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return -ECANCELED;
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@ -207,7 +207,7 @@ func_cont:
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* more IOR's.
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*/
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if (is_eos)
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pchnl->dw_state |= CHNL_STATEEOS;
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pchnl->state |= CHNL_STATEEOS;
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/* Legacy DSM Processor-Copy */
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DBC_ASSERT(pchnl->chnl_type == CHNL_PCPY);
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@ -258,7 +258,7 @@ int bridge_chnl_cancel_io(struct chnl_object *chnl_obj)
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* IORequests or dispatching. */
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spin_lock_bh(&chnl_mgr_obj->chnl_mgr_lock);
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pchnl->dw_state |= CHNL_STATECANCEL;
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pchnl->state |= CHNL_STATECANCEL;
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if (list_empty(&pchnl->pio_requests)) {
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spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
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@ -312,7 +312,7 @@ int bridge_chnl_close(struct chnl_object *chnl_obj)
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if (status)
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return status;
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/* Assert I/O on this channel is now cancelled: Protects from io_dpc */
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DBC_ASSERT((pchnl->dw_state & CHNL_STATECANCEL));
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DBC_ASSERT((pchnl->state & CHNL_STATECANCEL));
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/* Invalidate channel object: Protects from CHNL_GetIOCompletion() */
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/* Free the slot in the channel manager: */
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pchnl->chnl_mgr_obj->ap_channel[pchnl->chnl_id] = NULL;
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@ -381,7 +381,7 @@ int bridge_chnl_create(struct chnl_mgr **channel_mgr,
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* max_channels, GFP_KERNEL);
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if (chnl_mgr_obj->ap_channel) {
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/* Initialize chnl_mgr object */
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chnl_mgr_obj->dw_type = CHNL_TYPESM;
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chnl_mgr_obj->type = CHNL_TYPESM;
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chnl_mgr_obj->word_size = mgr_attrts->word_size;
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/* Total # chnls supported */
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chnl_mgr_obj->max_channels = max_channels;
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@ -488,7 +488,7 @@ int bridge_chnl_flush_io(struct chnl_object *chnl_obj, u32 timeout)
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} else {
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status = bridge_chnl_cancel_io(chnl_obj);
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/* Now, leave the channel in the ready state: */
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pchnl->dw_state &= ~CHNL_STATECANCEL;
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pchnl->state &= ~CHNL_STATECANCEL;
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}
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}
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DBC_ENSURE(status || list_empty(&pchnl->pio_requests));
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@ -517,7 +517,7 @@ int bridge_chnl_get_info(struct chnl_object *chnl_obj,
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channel_info->sync_event = pchnl->sync_event;
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channel_info->cio_cs = pchnl->cio_cs;
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channel_info->cio_reqs = pchnl->cio_reqs;
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channel_info->dw_state = pchnl->dw_state;
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channel_info->state = pchnl->state;
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} else {
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status = -EFAULT;
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}
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@ -687,7 +687,7 @@ int bridge_chnl_get_mgr_info(struct chnl_mgr *hchnl_mgr, u32 ch_id,
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/* Return the requested information: */
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mgr_info->chnl_obj = chnl_mgr_obj->ap_channel[ch_id];
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mgr_info->open_channels = chnl_mgr_obj->open_channels;
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mgr_info->dw_type = chnl_mgr_obj->dw_type;
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mgr_info->type = chnl_mgr_obj->type;
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/* total # of chnls */
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mgr_info->max_channels = chnl_mgr_obj->max_channels;
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@ -718,7 +718,7 @@ int bridge_chnl_idle(struct chnl_object *chnl_obj, u32 timeout,
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/* Reset the byte count and put channel back in ready state. */
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chnl_obj->bytes_moved = 0;
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chnl_obj->dw_state &= ~CHNL_STATECANCEL;
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chnl_obj->state &= ~CHNL_STATECANCEL;
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}
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return status;
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@ -769,7 +769,7 @@ int bridge_chnl_open(struct chnl_object **chnl,
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return -ENOMEM;
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/* Protect queues from io_dpc: */
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pchnl->dw_state = CHNL_STATECANCEL;
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pchnl->state = CHNL_STATECANCEL;
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/* Allocate initial IOR and IOC queues: */
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status = create_chirp_list(&pchnl->free_packets_list,
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@ -817,7 +817,7 @@ int bridge_chnl_open(struct chnl_object **chnl,
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chnl_mgr_obj->open_channels++;
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spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
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/* Return result... */
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pchnl->dw_state = CHNL_STATEREADY;
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pchnl->state = CHNL_STATEREADY;
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*chnl = pchnl;
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return status;
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@ -483,7 +483,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
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1)) == 0)) {
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status =
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hio_mgr->intf_fxns->
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pfn_brd_mem_map(hio_mgr->hbridge_context,
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brd_mem_map(hio_mgr->hbridge_context,
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pa_curr, va_curr,
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page_size[i], map_attrs,
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NULL);
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@ -549,7 +549,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
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} else {
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status =
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hio_mgr->intf_fxns->
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pfn_brd_mem_map(hio_mgr->hbridge_context,
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brd_mem_map(hio_mgr->hbridge_context,
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pa_curr, va_curr,
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page_size[i], map_attrs,
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NULL);
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@ -615,7 +615,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
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ae_proc[ndx].ul_dsp_va);
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ndx++;
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} else {
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status = hio_mgr->intf_fxns->pfn_brd_mem_map
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status = hio_mgr->intf_fxns->brd_mem_map
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(hio_mgr->hbridge_context,
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hio_mgr->ext_proc_info.ty_tlb[i].
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ul_gpp_phys,
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@ -637,7 +637,7 @@ int bridge_io_on_loaded(struct io_mgr *hio_mgr)
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/* Map the L4 peripherals */
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i = 0;
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while (l4_peripheral_table[i].phys_addr) {
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status = hio_mgr->intf_fxns->pfn_brd_mem_map
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status = hio_mgr->intf_fxns->brd_mem_map
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(hio_mgr->hbridge_context, l4_peripheral_table[i].phys_addr,
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l4_peripheral_table[i].dsp_virt_addr, HW_PAGE_SIZE4KB,
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map_attrs, NULL);
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@ -977,8 +977,8 @@ void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl,
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* Assertion fires if CHNL_AddIOReq() called on a stream
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* which was cancelled, or attached to a dead board.
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*/
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DBC_ASSERT((pchnl->dw_state == CHNL_STATEREADY) ||
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(pchnl->dw_state == CHNL_STATEEOS));
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DBC_ASSERT((pchnl->state == CHNL_STATEREADY) ||
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(pchnl->state == CHNL_STATEEOS));
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/* Indicate to the DSP we have a buffer available for input */
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set_chnl_busy(sm, pchnl->chnl_id);
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*mbx_val = MBX_PCPY_CLASS;
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@ -987,7 +987,7 @@ void io_request_chnl(struct io_mgr *io_manager, struct chnl_object *pchnl,
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* This assertion fails if CHNL_AddIOReq() was called on a
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* stream which was cancelled, or attached to a dead board.
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*/
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DBC_ASSERT((pchnl->dw_state & ~CHNL_STATEEOS) ==
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DBC_ASSERT((pchnl->state & ~CHNL_STATEEOS) ==
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CHNL_STATEREADY);
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/*
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* Record the fact that we have a buffer available for
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@ -1092,7 +1092,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
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}
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pchnl = chnl_mgr_obj->ap_channel[chnl_id];
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if ((pchnl != NULL) && CHNL_IS_INPUT(pchnl->chnl_mode)) {
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if ((pchnl->dw_state & ~CHNL_STATEEOS) == CHNL_STATEREADY) {
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if ((pchnl->state & ~CHNL_STATEEOS) == CHNL_STATEREADY) {
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/* Get the I/O request, and attempt a transfer */
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if (!list_empty(&pchnl->pio_requests)) {
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if (!pchnl->cio_reqs)
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@ -1122,7 +1122,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
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* sends EOS more than once on this
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* channel.
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*/
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if (pchnl->dw_state & CHNL_STATEEOS)
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if (pchnl->state & CHNL_STATEEOS)
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goto func_end;
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/*
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* Zero bytes indicates EOS. Update
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@ -1131,7 +1131,7 @@ static void input_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
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*/
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chnl_packet_obj->status |=
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CHNL_IOCSTATEOS;
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pchnl->dw_state |= CHNL_STATEEOS;
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pchnl->state |= CHNL_STATEEOS;
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/*
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* Notify that end of stream has
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* occurred.
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@ -1329,7 +1329,7 @@ static void output_chnl(struct io_mgr *pio_mgr, struct chnl_object *pchnl,
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if (sm->output_full)
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goto func_end;
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if (pchnl && !((pchnl->dw_state & ~CHNL_STATEEOS) == CHNL_STATEREADY))
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if (pchnl && !((pchnl->state & ~CHNL_STATEEOS) == CHNL_STATEREADY))
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goto func_end;
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/* Look to see if both a PC and DSP output channel are ready */
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@ -1810,7 +1810,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context)
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psz_buf = kzalloc(ul_num_bytes + 2, GFP_ATOMIC);
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if (psz_buf != NULL) {
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/* Read trace buffer data */
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status = (*intf_fxns->pfn_brd_read)(pbridge_context,
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status = (*intf_fxns->brd_read)(pbridge_context,
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(u8 *)psz_buf, (u32)ul_trace_begin,
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ul_num_bytes, 0);
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@ -1825,7 +1825,7 @@ int print_dsp_trace_buffer(struct bridge_dev_context *hbridge_context)
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__func__, psz_buf);
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/* Read the value at the DSP address in trace_cur_pos. */
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status = (*intf_fxns->pfn_brd_read)(pbridge_context,
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status = (*intf_fxns->brd_read)(pbridge_context,
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(u8 *)&trace_cur_pos, (u32)trace_cur_pos,
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4, 0);
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if (status)
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@ -1992,7 +1992,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context)
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poll_cnt < POLL_MAX) {
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/* Read DSP dump size from the DSP trace buffer... */
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status = (*intf_fxns->pfn_brd_read)(bridge_context,
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status = (*intf_fxns->brd_read)(bridge_context,
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(u8 *)&mmu_fault_dbg_info, (u32)trace_begin,
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sizeof(mmu_fault_dbg_info), 0);
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@ -2028,7 +2028,7 @@ int dump_dsp_stack(struct bridge_dev_context *bridge_context)
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buffer_end = buffer + total_size / 4;
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/* Read bytes from the DSP trace buffer... */
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status = (*intf_fxns->pfn_brd_read)(bridge_context,
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status = (*intf_fxns->brd_read)(bridge_context,
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(u8 *)buffer, (u32)trace_begin,
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total_size, 0);
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if (status) {
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@ -2189,7 +2189,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context)
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pr_debug("%s: _DLModules at 0x%x\n", __func__, module_dsp_addr);
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/* Copy the modules_header structure from DSP memory. */
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status = (*intf_fxns->pfn_brd_read)(bridge_context, (u8 *) &modules_hdr,
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status = (*intf_fxns->brd_read)(bridge_context, (u8 *) &modules_hdr,
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(u32) module_dsp_addr, sizeof(modules_hdr), 0);
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if (status) {
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@ -2224,7 +2224,7 @@ void dump_dl_modules(struct bridge_dev_context *bridge_context)
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goto func_end;
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}
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/* Copy the dll_module structure from DSP memory */
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status = (*intf_fxns->pfn_brd_read)(bridge_context,
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status = (*intf_fxns->brd_read)(bridge_context,
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(u8 *)module_struct, module_dsp_addr, module_size, 0);
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if (status) {
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@ -765,7 +765,7 @@ static int bridge_dev_create(struct bridge_dev_context
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}
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dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
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dev_context->dw_self_loop = (u32) NULL;
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dev_context->self_loop = (u32) NULL;
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dev_context->dsp_per_clks = 0;
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dev_context->internal_size = OMAP_DSP_SIZE;
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/* Clear dev context MMU table entries.
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@ -127,7 +127,7 @@ struct chnl_mgr {
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u8 max_channels; /* Total number of channels */
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u8 open_channels; /* Total number of open channels */
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struct chnl_object **ap_channel; /* Array of channels */
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u8 dw_type; /* Type of channel class library */
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u8 type; /* Type of channel class library */
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/* If no shm syms, return for CHNL_Open */
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int chnl_open_status;
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};
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@ -140,7 +140,7 @@ struct chnl_object {
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/* Pointer back to channel manager */
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struct chnl_mgr *chnl_mgr_obj;
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u32 chnl_id; /* Channel id */
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u8 dw_state; /* Current channel state */
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u8 state; /* Current channel state */
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s8 chnl_mode; /* Chnl mode and attributes */
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/* Chnl I/O completion event (user mode) */
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void *user_event;
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@ -59,7 +59,7 @@ struct chnl_info {
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/*Abstraction of I/O completion event. */
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struct sync_object *sync_event;
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s8 mode; /* Channel mode. */
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u8 dw_state; /* Current channel state. */
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u8 state; /* Current channel state. */
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u32 bytes_tx; /* Total bytes transferred. */
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u32 cio_cs; /* Number of IOCs in queue. */
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u32 cio_reqs; /* Number of IO Requests in queue. */
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@ -68,7 +68,7 @@ struct chnl_info {
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/* Channel manager info: */
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struct chnl_mgrinfo {
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u8 dw_type; /* Type of channel class library. */
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u8 type; /* Type of channel class library. */
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/* Channel handle, given the channel id. */
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struct chnl_object *chnl_obj;
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u8 open_channels; /* Number of open channels. */
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@ -60,7 +60,7 @@ struct cmm_seginfo {
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u32 ul_dsp_size; /* DSP seg size in bytes */
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/* # of current GPP allocations from this segment */
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u32 ul_in_use_cnt;
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u32 dw_seg_base_va; /* Start Virt address of SM seg */
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u32 seg_base_va; /* Start Virt address of SM seg */
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};
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@ -83,8 +83,8 @@ struct cmm_xlatorattrs {
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u32 dsp_buf_size; /* size of DSP-side bufs in GPP bytes */
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/* Vm base address alloc'd in client process context */
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void *vm_base;
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/* dw_vm_size must be >= (dwMaxNumBufs * dwMaxSize) */
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u32 dw_vm_size;
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/* vm_size must be >= (dwMaxNumBufs * dwMaxSize) */
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u32 vm_size;
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};
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/*
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@ -369,9 +369,9 @@ struct dsp_processorinfo {
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/* Error information of last DSP exception signalled to the GPP */
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struct dsp_errorinfo {
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u32 err_mask;
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u32 dw_val1;
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u32 dw_val2;
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u32 dw_val3;
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u32 val1;
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u32 val2;
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u32 val3;
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};
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/* The dsp_processorstate structure describes the state of a DSP processor */
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@ -978,17 +978,17 @@ struct bridge_drv_interface {
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fxn_dev_create pfn_dev_create; /* Create device context */
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fxn_dev_destroy pfn_dev_destroy; /* Destroy device context */
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fxn_dev_ctrl pfn_dev_cntrl; /* Optional vendor interface */
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fxn_brd_monitor pfn_brd_monitor; /* Load and/or start monitor */
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fxn_brd_monitor brd_monitor; /* Load and/or start monitor */
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fxn_brd_start pfn_brd_start; /* Start DSP program. */
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fxn_brd_stop pfn_brd_stop; /* Stop/reset board. */
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fxn_brd_status pfn_brd_status; /* Get current board status. */
|
||||
fxn_brd_read pfn_brd_read; /* Read board memory */
|
||||
fxn_brd_read brd_read; /* Read board memory */
|
||||
fxn_brd_write pfn_brd_write; /* Write board memory. */
|
||||
fxn_brd_setstate pfn_brd_set_state; /* Sets the Board State */
|
||||
fxn_brd_memcopy pfn_brd_mem_copy; /* Copies DSP Memory */
|
||||
fxn_brd_memwrite pfn_brd_mem_write; /* Write DSP Memory w/o halt */
|
||||
fxn_brd_memmap pfn_brd_mem_map; /* Maps MPU mem to DSP mem */
|
||||
fxn_brd_memunmap pfn_brd_mem_un_map; /* Unmaps MPU mem to DSP mem */
|
||||
fxn_brd_memcopy brd_mem_copy; /* Copies DSP Memory */
|
||||
fxn_brd_memwrite brd_mem_write; /* Write DSP Memory w/o halt */
|
||||
fxn_brd_memmap brd_mem_map; /* Maps MPU mem to DSP mem */
|
||||
fxn_brd_memunmap brd_mem_un_map; /* Unmaps MPU mem to DSP mem */
|
||||
fxn_chnl_create pfn_chnl_create; /* Create channel manager. */
|
||||
fxn_chnl_destroy pfn_chnl_destroy; /* Destroy channel manager. */
|
||||
fxn_chnl_open pfn_chnl_open; /* Create a new channel. */
|
||||
|
|
|
@ -280,7 +280,7 @@ typedef int(*nldr_unloadfxn) (struct nldr_nodeobject *nldr_node_obj,
|
|||
* ======== node_ldr_fxns ========
|
||||
*/
|
||||
struct node_ldr_fxns {
|
||||
nldr_allocatefxn pfn_allocate;
|
||||
nldr_allocatefxn allocate;
|
||||
nldr_createfxn pfn_create;
|
||||
nldr_deletefxn pfn_delete;
|
||||
nldr_exitfxn pfn_exit;
|
||||
|
|
|
@ -64,7 +64,7 @@
|
|||
struct cmm_allocator { /* sma */
|
||||
unsigned int shm_base; /* Start of physical SM block */
|
||||
u32 ul_sm_size; /* Size of SM block in bytes */
|
||||
unsigned int dw_vm_base; /* Start of VM block. (Dev driver
|
||||
unsigned int vm_base; /* Start of VM block. (Dev driver
|
||||
* context for 'sma') */
|
||||
u32 dsp_phys_addr_offset; /* DSP PA to GPP PA offset for this
|
||||
* SM space */
|
||||
|
@ -86,7 +86,7 @@ struct cmm_xlator { /* Pa<->Va translator object */
|
|||
* base address for translator's ul_seg_id.
|
||||
* Only 1 segment ID currently supported.
|
||||
*/
|
||||
unsigned int dw_virt_base; /* virtual base address */
|
||||
unsigned int virt_base; /* virtual base address */
|
||||
u32 ul_virt_size; /* size of virt space in bytes */
|
||||
u32 ul_seg_id; /* Segment Id */
|
||||
};
|
||||
|
@ -122,14 +122,14 @@ static struct cmm_xlatorattrs cmm_dfltxlatorattrs = {
|
|||
0, /* dsp_bufs */
|
||||
0, /* dsp_buf_size */
|
||||
NULL, /* vm_base */
|
||||
0, /* dw_vm_size */
|
||||
0, /* vm_size */
|
||||
};
|
||||
|
||||
/* SM node representing a block of memory. */
|
||||
struct cmm_mnode {
|
||||
struct list_head link; /* must be 1st element */
|
||||
u32 pa; /* Phys addr */
|
||||
u32 dw_va; /* Virtual address in device process context */
|
||||
u32 va; /* Virtual address in device process context */
|
||||
u32 ul_size; /* SM block size in bytes */
|
||||
u32 client_proc; /* Process that allocated this mem block */
|
||||
};
|
||||
|
@ -200,7 +200,7 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize,
|
|||
* add to freelist */
|
||||
new_node =
|
||||
get_node(cmm_mgr_obj, pnode->pa + usize,
|
||||
pnode->dw_va + usize,
|
||||
pnode->va + usize,
|
||||
(u32) delta_size);
|
||||
/* leftovers go free */
|
||||
add_to_free_list(allocator, new_node);
|
||||
|
@ -218,13 +218,13 @@ void *cmm_calloc_buf(struct cmm_object *hcmm_mgr, u32 usize,
|
|||
list_add_tail(&pnode->link, &allocator->in_use_list);
|
||||
buf_pa = (void *)pnode->pa; /* physical address */
|
||||
/* clear mem */
|
||||
pbyte = (u8 *) pnode->dw_va;
|
||||
pbyte = (u8 *) pnode->va;
|
||||
for (cnt = 0; cnt < (s32) usize; cnt++, pbyte++)
|
||||
*pbyte = 0;
|
||||
|
||||
if (pp_buf_va != NULL) {
|
||||
/* Virtual address */
|
||||
*pp_buf_va = (void *)pnode->dw_va;
|
||||
*pp_buf_va = (void *)pnode->va;
|
||||
}
|
||||
}
|
||||
mutex_unlock(&cmm_mgr_obj->cmm_lock);
|
||||
|
@ -450,8 +450,8 @@ int cmm_get_info(struct cmm_object *hcmm_mgr,
|
|||
altr->dsp_base;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].ul_dsp_size =
|
||||
altr->ul_dsp_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].dw_seg_base_va =
|
||||
altr->dw_vm_base - altr->ul_dsp_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].seg_base_va =
|
||||
altr->vm_base - altr->ul_dsp_size;
|
||||
cmm_info_obj->seg_info[ul_seg - 1].ul_in_use_cnt = 0;
|
||||
|
||||
list_for_each_entry(curr, &altr->in_use_list, link) {
|
||||
|
@ -539,12 +539,12 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr,
|
|||
psma->hcmm_mgr = hcmm_mgr; /* ref to parent */
|
||||
psma->shm_base = dw_gpp_base_pa; /* SM Base phys */
|
||||
psma->ul_sm_size = ul_size; /* SM segment size in bytes */
|
||||
psma->dw_vm_base = gpp_base_va;
|
||||
psma->vm_base = gpp_base_va;
|
||||
psma->dsp_phys_addr_offset = dsp_addr_offset;
|
||||
psma->c_factor = c_factor;
|
||||
psma->dsp_base = dw_dsp_base;
|
||||
psma->ul_dsp_size = ul_dsp_size;
|
||||
if (psma->dw_vm_base == 0) {
|
||||
if (psma->vm_base == 0) {
|
||||
status = -EPERM;
|
||||
goto func_end;
|
||||
}
|
||||
|
@ -556,7 +556,7 @@ int cmm_register_gppsm_seg(struct cmm_object *hcmm_mgr,
|
|||
|
||||
/* Get a mem node for this hunk-o-memory */
|
||||
new_node = get_node(cmm_mgr_obj, dw_gpp_base_pa,
|
||||
psma->dw_vm_base, ul_size);
|
||||
psma->vm_base, ul_size);
|
||||
/* Place node on the SM allocator's free list */
|
||||
if (new_node) {
|
||||
list_add_tail(&new_node->link, &psma->free_list);
|
||||
|
@ -649,8 +649,8 @@ static void un_register_gppsm_seg(struct cmm_allocator *psma)
|
|||
kfree(curr);
|
||||
}
|
||||
|
||||
if ((void *)psma->dw_vm_base != NULL)
|
||||
MEM_UNMAP_LINEAR_ADDRESS((void *)psma->dw_vm_base);
|
||||
if ((void *)psma->vm_base != NULL)
|
||||
MEM_UNMAP_LINEAR_ADDRESS((void *)psma->vm_base);
|
||||
|
||||
/* Free allocator itself */
|
||||
kfree(psma);
|
||||
|
@ -705,7 +705,7 @@ static struct cmm_mnode *get_node(struct cmm_object *cmm_mgr_obj, u32 dw_pa,
|
|||
}
|
||||
|
||||
pnode->pa = dw_pa;
|
||||
pnode->dw_va = dw_va;
|
||||
pnode->va = dw_va;
|
||||
pnode->ul_size = ul_size;
|
||||
|
||||
return pnode;
|
||||
|
@ -770,7 +770,7 @@ static void add_to_free_list(struct cmm_allocator *allocator,
|
|||
}
|
||||
if (curr->pa == NEXT_PA(node)) {
|
||||
curr->pa = node->pa;
|
||||
curr->dw_va = node->dw_va;
|
||||
curr->va = node->va;
|
||||
curr->ul_size += node->ul_size;
|
||||
delete_node(allocator->hcmm_mgr, node);
|
||||
return;
|
||||
|
@ -925,10 +925,10 @@ int cmm_xlator_info(struct cmm_xlatorobject *xlator, u8 ** paddr,
|
|||
if (xlator_obj) {
|
||||
if (set_info) {
|
||||
/* set translators virtual address range */
|
||||
xlator_obj->dw_virt_base = (u32) *paddr;
|
||||
xlator_obj->virt_base = (u32) *paddr;
|
||||
xlator_obj->ul_virt_size = ul_size;
|
||||
} else { /* return virt base address */
|
||||
*paddr = (u8 *) xlator_obj->dw_virt_base;
|
||||
*paddr = (u8 *) xlator_obj->virt_base;
|
||||
}
|
||||
} else {
|
||||
status = -EFAULT;
|
||||
|
@ -969,18 +969,18 @@ void *cmm_xlator_translate(struct cmm_xlatorobject *xlator, void *paddr,
|
|||
dw_offset = (u8 *) paddr - (u8 *) (allocator->shm_base -
|
||||
allocator->
|
||||
ul_dsp_size);
|
||||
dw_addr_xlate = xlator_obj->dw_virt_base + dw_offset;
|
||||
dw_addr_xlate = xlator_obj->virt_base + dw_offset;
|
||||
/* Check if translated Va base is in range */
|
||||
if ((dw_addr_xlate < xlator_obj->dw_virt_base) ||
|
||||
if ((dw_addr_xlate < xlator_obj->virt_base) ||
|
||||
(dw_addr_xlate >=
|
||||
(xlator_obj->dw_virt_base +
|
||||
(xlator_obj->virt_base +
|
||||
xlator_obj->ul_virt_size))) {
|
||||
dw_addr_xlate = 0; /* bad address */
|
||||
}
|
||||
} else {
|
||||
/* Gpp PA = Gpp Base + offset */
|
||||
dw_offset =
|
||||
(u8 *) paddr - (u8 *) xlator_obj->dw_virt_base;
|
||||
(u8 *) paddr - (u8 *) xlator_obj->virt_base;
|
||||
dw_addr_xlate =
|
||||
allocator->shm_base - allocator->ul_dsp_size +
|
||||
dw_offset;
|
||||
|
|
|
@ -1082,17 +1082,17 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns,
|
|||
STORE_FXN(fxn_dev_create, pfn_dev_create);
|
||||
STORE_FXN(fxn_dev_destroy, pfn_dev_destroy);
|
||||
STORE_FXN(fxn_dev_ctrl, pfn_dev_cntrl);
|
||||
STORE_FXN(fxn_brd_monitor, pfn_brd_monitor);
|
||||
STORE_FXN(fxn_brd_monitor, brd_monitor);
|
||||
STORE_FXN(fxn_brd_start, pfn_brd_start);
|
||||
STORE_FXN(fxn_brd_stop, pfn_brd_stop);
|
||||
STORE_FXN(fxn_brd_status, pfn_brd_status);
|
||||
STORE_FXN(fxn_brd_read, pfn_brd_read);
|
||||
STORE_FXN(fxn_brd_read, brd_read);
|
||||
STORE_FXN(fxn_brd_write, pfn_brd_write);
|
||||
STORE_FXN(fxn_brd_setstate, pfn_brd_set_state);
|
||||
STORE_FXN(fxn_brd_memcopy, pfn_brd_mem_copy);
|
||||
STORE_FXN(fxn_brd_memwrite, pfn_brd_mem_write);
|
||||
STORE_FXN(fxn_brd_memmap, pfn_brd_mem_map);
|
||||
STORE_FXN(fxn_brd_memunmap, pfn_brd_mem_un_map);
|
||||
STORE_FXN(fxn_brd_memcopy, brd_mem_copy);
|
||||
STORE_FXN(fxn_brd_memwrite, brd_mem_write);
|
||||
STORE_FXN(fxn_brd_memmap, brd_mem_map);
|
||||
STORE_FXN(fxn_brd_memunmap, brd_mem_un_map);
|
||||
STORE_FXN(fxn_chnl_create, pfn_chnl_create);
|
||||
STORE_FXN(fxn_chnl_destroy, pfn_chnl_destroy);
|
||||
STORE_FXN(fxn_chnl_open, pfn_chnl_open);
|
||||
|
@ -1123,11 +1123,11 @@ static void store_interface_fxns(struct bridge_drv_interface *drv_fxns,
|
|||
DBC_ENSURE(intf_fxns->pfn_dev_create != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_dev_destroy != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_dev_cntrl != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_brd_monitor != NULL);
|
||||
DBC_ENSURE(intf_fxns->brd_monitor != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_brd_start != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_brd_stop != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_brd_status != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_brd_read != NULL);
|
||||
DBC_ENSURE(intf_fxns->brd_read != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_brd_write != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_chnl_create != NULL);
|
||||
DBC_ENSURE(intf_fxns->pfn_chnl_destroy != NULL);
|
||||
|
|
|
@ -575,7 +575,7 @@ func_cont:
|
|||
if (!status) {
|
||||
/* Create object for dynamic loading */
|
||||
|
||||
status = hnode_mgr->nldr_fxns.pfn_allocate(hnode_mgr->nldr_obj,
|
||||
status = hnode_mgr->nldr_fxns.allocate(hnode_mgr->nldr_obj,
|
||||
(void *)pnode,
|
||||
&pnode->dcd_props.
|
||||
obj_data.node_obj,
|
||||
|
@ -3075,7 +3075,7 @@ static u32 ovly(void *priv_ref, u32 dsp_run_addr, u32 dsp_load_addr,
|
|||
status = dev_get_bridge_context(hnode_mgr->hdev_obj, &hbridge_context);
|
||||
if (!status) {
|
||||
status =
|
||||
(*intf_fxns->pfn_brd_mem_copy) (hbridge_context,
|
||||
(*intf_fxns->brd_mem_copy) (hbridge_context,
|
||||
dsp_run_addr, dsp_load_addr,
|
||||
ul_num_bytes, (u32) mem_space);
|
||||
if (!status)
|
||||
|
@ -3117,7 +3117,7 @@ static u32 mem_write(void *priv_ref, u32 dsp_add, void *pbuf,
|
|||
/* Call new MemWrite function */
|
||||
intf_fxns = hnode_mgr->intf_fxns;
|
||||
status = dev_get_bridge_context(hnode_mgr->hdev_obj, &hbridge_context);
|
||||
status = (*intf_fxns->pfn_brd_mem_write) (hbridge_context, pbuf,
|
||||
status = (*intf_fxns->brd_mem_write) (hbridge_context, pbuf,
|
||||
dsp_add, ul_num_bytes, mem_sect_type);
|
||||
|
||||
return ul_num_bytes;
|
||||
|
|
|
@ -1397,7 +1397,7 @@ int proc_map(void *hprocessor, void *pmpu_addr, u32 ul_size,
|
|||
if (!map_obj)
|
||||
status = -ENOMEM;
|
||||
else
|
||||
status = (*p_proc_object->intf_fxns->pfn_brd_mem_map)
|
||||
status = (*p_proc_object->intf_fxns->brd_mem_map)
|
||||
(p_proc_object->hbridge_context, pa_align, va_align,
|
||||
size_align, ul_map_attr, map_obj->pages);
|
||||
}
|
||||
|
@ -1720,7 +1720,7 @@ int proc_un_map(void *hprocessor, void *map_addr,
|
|||
status = dmm_un_map_memory(dmm_mgr, (u32) va_align, &size_align);
|
||||
/* Remove mapping from the page tables. */
|
||||
if (!status) {
|
||||
status = (*p_proc_object->intf_fxns->pfn_brd_mem_un_map)
|
||||
status = (*p_proc_object->intf_fxns->brd_mem_un_map)
|
||||
(p_proc_object->hbridge_context, va_align, size_align);
|
||||
}
|
||||
|
||||
|
@ -1828,7 +1828,7 @@ static int proc_monitor(struct proc_object *proc_obj)
|
|||
}
|
||||
}
|
||||
/* Place the Board in the Monitor State */
|
||||
if (!((*proc_obj->intf_fxns->pfn_brd_monitor)
|
||||
if (!((*proc_obj->intf_fxns->brd_monitor)
|
||||
(proc_obj->hbridge_context))) {
|
||||
status = 0;
|
||||
if (!((*proc_obj->intf_fxns->pfn_brd_status)
|
||||
|
|
|
@ -344,7 +344,7 @@ int strm_get_info(struct strm_object *stream_obj,
|
|||
stream_info->user_strm->ul_number_bytes = chnl_info_obj.bytes_tx;
|
||||
stream_info->user_strm->sync_object_handle = chnl_info_obj.event_obj;
|
||||
/* Determine stream state based on channel state and info */
|
||||
if (chnl_info_obj.dw_state & CHNL_STATEEOS) {
|
||||
if (chnl_info_obj.state & CHNL_STATEEOS) {
|
||||
stream_info->user_strm->ss_stream_state = STREAM_DONE;
|
||||
} else {
|
||||
if (chnl_info_obj.cio_cs > 0)
|
||||
|
|
Loading…
Reference in a new issue