The i.MX clock updates for 4.4:
- A couple of fixes on i.MX31 and i.MX35 clock initialization functions which makes mxc_timer_init() currently be called twice for DT boot. - Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal design target. - Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for Vybrid, and SPDIF_GCLK for i.MX6. - A series from Lucas to fix early debug UART clock setup. This is currently a one-off fix for i.MX platform, and can be extended to become a generic solution later. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJWIRFyAAoJEFBXWFqHsHzOE7wH/25WaamOOOL3vGVCBeIs2+aB nibCEKCPGu2/b1YN+BEQMlh+K7d59Ogd0xVtTkLEGhIBW+LF5zDpsd6jNl7Ts6PQ 5w3gG7K/NqPzIXlgo+z5Oa4UI1DlDemcA1xihR+hFWjLQb8DBmnusK52ctS5MLfP 6SoepDWHJvtuAfoL/3ytNTi/xCW12sEVkzRV7QbG9GV2UmUgF2AVWKBkH+c28vnP dyt2Cyrr4+9ov6p0k0OJnHDv1AxkkNlHh0G33pZMZmnqcn/ZagmdH2GReGWZi6PM XLMY/piEK7zzryJ51hL9AGZi7so1LWs27kBtYo9r7bN9/cG4kaENGw6Du1jEf4I= =OBCO -----END PGP SIGNATURE----- Merge tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next Pull i.MX updates from Shawn Guo: "The i.MX clock updates for 4.4: - A couple of fixes on i.MX31 and i.MX35 clock initialization functions which makes mxc_timer_init() currently be called twice for DT boot. - Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal design target. - Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for Vybrid, and SPDIF_GCLK for i.MX6. - A series from Lucas to fix early debug UART clock setup. This is currently a one-off fix for i.MX platform, and can be extended to become a generic solution later." * tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: clk: imx6: Add SPDIF_GCLK clock in clock tree clk: imx7d: add ADC root clock clk: imx31: Do not call mxc_timer_init twice when booting with DT clk: imx7d: retain early UART clocks during kernel init clk: imx6: retain early UART clocks during kernel init clk: imx5: retain early UART clocks during kernel init clk: imx35: retain early UART clocks during kernel init clk: imx31: retain early UART clocks during kernel init clk: imx27: retain early UART clocks during kernel init clk: imx25: retain early UART clocks during kernel init clk: imx: add common logic to detect early UART usage clk: imx35: Do not call mxc_timer_init twice when booting with DT clk: clk-vf610: Add clock for Vybrid OCOTP controller clk: imx: increase AXI clock rate to 264MHz for i.MX6UL
This commit is contained in:
commit
3ce6c6e541
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@ -86,6 +86,16 @@ enum mx25_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[uart_ipg_per],
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&clk[uart1_ipg],
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&clk[uart2_ipg],
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&clk[uart3_ipg],
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&clk[uart4_ipg],
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&clk[uart5_ipg],
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NULL
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};
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static int __init __mx25_clocks_init(unsigned long osc_rate,
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void __iomem *ccm_base)
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{
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@ -233,6 +243,8 @@ static int __init __mx25_clocks_init(unsigned long osc_rate,
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*/
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clk_set_parent(clk[cko_sel], clk[ipg]);
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imx_register_uart_clocks(uart_clks);
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return 0;
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}
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@ -47,6 +47,17 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks[] __initconst = {
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&clk[IMX27_CLK_PER1_GATE],
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&clk[IMX27_CLK_UART1_IPG_GATE],
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&clk[IMX27_CLK_UART2_IPG_GATE],
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&clk[IMX27_CLK_UART3_IPG_GATE],
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&clk[IMX27_CLK_UART4_IPG_GATE],
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&clk[IMX27_CLK_UART5_IPG_GATE],
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&clk[IMX27_CLK_UART6_IPG_GATE],
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NULL
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};
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static void __init _mx27_clocks_init(unsigned long fref)
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{
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BUG_ON(!ccm);
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@ -163,6 +174,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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imx_register_uart_clocks(uart_clks);
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imx_print_silicon_rev("i.MX27", mx27_revision());
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}
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@ -62,7 +62,17 @@ enum mx31_clks {
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static struct clk *clk[clk_max];
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static struct clk_onecell_data clk_data;
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int __init mx31_clocks_init(unsigned long fref)
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static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
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&clk[uart1_gate],
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&clk[uart2_gate],
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&clk[uart3_gate],
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&clk[uart4_gate],
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&clk[uart5_gate],
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NULL
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};
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static void __init _mx31_clocks_init(unsigned long fref)
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{
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void __iomem *base;
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struct device_node *np;
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@ -132,6 +142,12 @@ int __init mx31_clocks_init(unsigned long fref)
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imx_check_clocks(clk, ARRAY_SIZE(clk));
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clk_set_parent(clk[csi], clk[upll]);
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clk_prepare_enable(clk[emi_gate]);
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clk_prepare_enable(clk[iim_gate]);
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mx31_revision();
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clk_disable_unprepare(clk[iim_gate]);
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np = of_find_compatible_node(NULL, NULL, "fsl,imx31-ccm");
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if (np) {
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@ -139,6 +155,13 @@ int __init mx31_clocks_init(unsigned long fref)
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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}
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int __init mx31_clocks_init(void)
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{
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u32 fref = 26000000; /* default */
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_mx31_clocks_init(fref);
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clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
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clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
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@ -194,12 +217,8 @@ int __init mx31_clocks_init(unsigned long fref)
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clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
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clk_register_clkdev(clk[iim_gate], "iim", NULL);
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clk_set_parent(clk[csi], clk[upll]);
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clk_prepare_enable(clk[emi_gate]);
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clk_prepare_enable(clk[iim_gate]);
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mx31_revision();
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clk_disable_unprepare(clk[iim_gate]);
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imx_register_uart_clocks(uart_clks);
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mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT, GPT_TYPE_IMX31);
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return 0;
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@ -218,5 +237,7 @@ int __init mx31_clocks_init_dt(void)
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break;
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}
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return mx31_clocks_init(fref);
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_mx31_clocks_init(fref);
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return 0;
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}
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@ -84,7 +84,15 @@ enum mx35_clks {
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static struct clk *clk[clk_max];
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int __init mx35_clocks_init(void)
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static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
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&clk[uart1_gate],
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&clk[uart2_gate],
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&clk[uart3_gate],
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NULL
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};
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static void __init _mx35_clocks_init(void)
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{
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void __iomem *base;
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u32 pdr0, consumer_sel, hsp_sel;
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@ -220,6 +228,32 @@ int __init mx35_clocks_init(void)
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imx_check_clocks(clk, ARRAY_SIZE(clk));
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clk_prepare_enable(clk[spba_gate]);
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clk_prepare_enable(clk[gpio1_gate]);
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clk_prepare_enable(clk[gpio2_gate]);
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clk_prepare_enable(clk[gpio3_gate]);
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clk_prepare_enable(clk[iim_gate]);
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clk_prepare_enable(clk[emi_gate]);
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clk_prepare_enable(clk[max_gate]);
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clk_prepare_enable(clk[iomuxc_gate]);
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/*
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* SCC is needed to boot via mmc after a watchdog reset. The clock code
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* before conversion to common clk also enabled UART1 (which isn't
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* handled here and not needed for mmc) and IIM (which is enabled
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* unconditionally above).
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_register_uart_clocks(uart_clks);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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}
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int __init mx35_clocks_init(void)
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{
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_mx35_clocks_init();
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clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
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clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
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clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
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@ -279,25 +313,6 @@ int __init mx35_clocks_init(void)
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clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
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clk_register_clkdev(clk[admux_gate], "audmux", NULL);
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clk_prepare_enable(clk[spba_gate]);
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clk_prepare_enable(clk[gpio1_gate]);
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clk_prepare_enable(clk[gpio2_gate]);
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clk_prepare_enable(clk[gpio3_gate]);
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clk_prepare_enable(clk[iim_gate]);
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clk_prepare_enable(clk[emi_gate]);
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clk_prepare_enable(clk[max_gate]);
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clk_prepare_enable(clk[iomuxc_gate]);
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/*
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* SCC is needed to boot via mmc after a watchdog reset. The clock code
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* before conversion to common clk also enabled UART1 (which isn't
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* handled here and not needed for mmc) and IIM (which is enabled
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* unconditionally above).
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
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return 0;
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@ -305,10 +320,10 @@ int __init mx35_clocks_init(void)
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static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
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{
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_mx35_clocks_init();
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
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mx35_clocks_init();
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}
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CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
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@ -130,6 +130,20 @@ static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
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static struct clk *clk[IMX5_CLK_END];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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&clk[IMX5_CLK_UART4_IPG_GATE],
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&clk[IMX5_CLK_UART4_PER_GATE],
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&clk[IMX5_CLK_UART5_IPG_GATE],
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&clk[IMX5_CLK_UART5_PER_GATE],
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NULL
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};
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static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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{
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clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@ -310,6 +324,8 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
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clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
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clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
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imx_register_uart_clocks(uart_clks);
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}
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static void __init mx50_clocks_init(struct device_node *np)
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@ -119,6 +119,7 @@ static unsigned int share_count_ssi1;
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static unsigned int share_count_ssi2;
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static unsigned int share_count_ssi3;
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static unsigned int share_count_mipi_core_cfg;
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static unsigned int share_count_spdif;
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static inline int clk_on_imx6q(void)
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{
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@ -130,6 +131,12 @@ static inline int clk_on_imx6dl(void)
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return of_machine_is_compatible("fsl,imx6dl");
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}
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static struct clk ** const uart_clks[] __initconst = {
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&clk[IMX6QDL_CLK_UART_IPG],
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&clk[IMX6QDL_CLK_UART_SERIAL],
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NULL
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};
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static void __init imx6q_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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@ -456,7 +463,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4);
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clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
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clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
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clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
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clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
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clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
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clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
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clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
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clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
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|
@ -541,5 +549,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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/* All existing boards with PCIe use LVDS1 */
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if (IS_ENABLED(CONFIG_PCI_IMX6))
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clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
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imx_register_uart_clocks(uart_clks);
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}
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CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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|
|
|
@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
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static unsigned int share_count_ssi1;
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static unsigned int share_count_ssi2;
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static unsigned int share_count_ssi3;
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static unsigned int share_count_spdif;
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static struct clk *clks[IMX6SL_CLK_END];
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static struct clk_onecell_data clk_data;
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|
@ -184,6 +185,12 @@ void imx6sl_set_wait_clk(bool enter)
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imx6sl_enable_pll_arm(false);
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}
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static struct clk ** const uart_clks[] __initconst = {
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&clks[IMX6SL_CLK_UART],
|
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&clks[IMX6SL_CLK_UART_SERIAL],
|
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NULL
|
||||
};
|
||||
|
||||
static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
@ -391,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
|
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clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
|
||||
clks[IMX6SL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
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clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
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||||
clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif0_podf", base + 0x7c, 14, &share_count_spdif);
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||||
clks[IMX6SL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
|
||||
clks[IMX6SL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
|
@ -439,5 +447,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
|
||||
clks[IMX6SL_CLK_PLL2_PFD2]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
|
||||
|
|
|
@ -135,6 +135,12 @@ static u32 share_count_ssi1;
|
|||
static u32 share_count_ssi2;
|
||||
static u32 share_count_ssi3;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clks[IMX6SX_CLK_UART_IPG],
|
||||
&clks[IMX6SX_CLK_UART_SERIAL],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
@ -454,6 +460,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
|
||||
clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio);
|
||||
clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
|
||||
clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
|
||||
clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
|
||||
|
@ -557,5 +564,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
}
|
||||
CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
|
||||
|
|
|
@ -407,6 +407,24 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
|
|||
clk_data.clk_num = ARRAY_SIZE(clks);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
/*
|
||||
* Lower the AHB clock rate before changing the parent clock source,
|
||||
* as AHB clock rate can NOT be higher than 133MHz, but its parent
|
||||
* will be switched from 396MHz PFD to 528MHz PLL in order to increase
|
||||
* AXI clock rate, so we need to lower AHB rate first to make sure at
|
||||
* any time, AHB rate is <= 133MHz.
|
||||
*/
|
||||
clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);
|
||||
|
||||
/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);
|
||||
|
||||
/* Make sure AHB rate is 132MHz */
|
||||
clk_set_rate(clks[IMX6UL_CLK_AHB], 132000000);
|
||||
|
||||
/* set perclk to from OSC */
|
||||
clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]);
|
||||
|
||||
|
|
|
@ -363,6 +363,17 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
|
|||
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static struct clk ** const uart_clks[] __initconst = {
|
||||
&clks[IMX7D_UART1_ROOT_CLK],
|
||||
&clks[IMX7D_UART2_ROOT_CLK],
|
||||
&clks[IMX7D_UART3_ROOT_CLK],
|
||||
&clks[IMX7D_UART4_ROOT_CLK],
|
||||
&clks[IMX7D_UART5_ROOT_CLK],
|
||||
&clks[IMX7D_UART6_ROOT_CLK],
|
||||
&clks[IMX7D_UART7_ROOT_CLK],
|
||||
NULL
|
||||
};
|
||||
|
||||
static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
@ -818,6 +829,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate2("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
|
||||
clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate2("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
|
||||
clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate2("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
|
||||
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate2("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
|
||||
|
||||
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
|
||||
|
||||
|
@ -856,5 +868,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
/* set uart module clock's parent clock source that must be great then 80MHz */
|
||||
clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
|
||||
}
|
||||
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
|
||||
|
|
|
@ -387,6 +387,7 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7));
|
||||
clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24);
|
||||
clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5));
|
||||
|
||||
imx_check_clocks(clk, ARRAY_SIZE(clk));
|
||||
|
||||
|
|
|
@ -73,3 +73,41 @@ void imx_cscmr1_fixup(u32 *val)
|
|||
*val ^= CSCMR1_FIXUP;
|
||||
return;
|
||||
}
|
||||
|
||||
static int imx_keep_uart_clocks __initdata;
|
||||
static struct clk ** const *imx_uart_clocks __initdata;
|
||||
|
||||
static int __init imx_keep_uart_clocks_param(char *str)
|
||||
{
|
||||
imx_keep_uart_clocks = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
__setup_param("earlycon", imx_keep_uart_earlycon,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
|
||||
void __init imx_register_uart_clocks(struct clk ** const clks[])
|
||||
{
|
||||
if (imx_keep_uart_clocks) {
|
||||
int i;
|
||||
|
||||
imx_uart_clocks = clks;
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_prepare_enable(*imx_uart_clocks[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static int __init imx_clk_disable_uart(void)
|
||||
{
|
||||
if (imx_keep_uart_clocks && imx_uart_clocks) {
|
||||
int i;
|
||||
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_disable_unprepare(*imx_uart_clocks[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
late_initcall_sync(imx_clk_disable_uart);
|
||||
|
|
|
@ -7,6 +7,7 @@
|
|||
extern spinlock_t imx_ccm_lock;
|
||||
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
|
||||
extern void imx_cscmr1_fixup(u32 *val);
|
||||
|
||||
|
|
|
@ -254,6 +254,7 @@
|
|||
#define IMX6QDL_CLK_CAAM_MEM 241
|
||||
#define IMX6QDL_CLK_CAAM_ACLK 242
|
||||
#define IMX6QDL_CLK_CAAM_IPG 243
|
||||
#define IMX6QDL_CLK_END 244
|
||||
#define IMX6QDL_CLK_SPDIF_GCLK 244
|
||||
#define IMX6QDL_CLK_END 245
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
|
||||
|
|
|
@ -174,6 +174,7 @@
|
|||
#define IMX6SL_CLK_SSI1_IPG 161
|
||||
#define IMX6SL_CLK_SSI2_IPG 162
|
||||
#define IMX6SL_CLK_SSI3_IPG 163
|
||||
#define IMX6SL_CLK_END 164
|
||||
#define IMX6SL_CLK_SPDIF_GCLK 164
|
||||
#define IMX6SL_CLK_END 165
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */
|
||||
|
|
|
@ -274,6 +274,7 @@
|
|||
#define IMX6SX_PLL5_BYPASS 261
|
||||
#define IMX6SX_PLL6_BYPASS 262
|
||||
#define IMX6SX_PLL7_BYPASS 263
|
||||
#define IMX6SX_CLK_CLK_END 264
|
||||
#define IMX6SX_CLK_SPDIF_GCLK 264
|
||||
#define IMX6SX_CLK_CLK_END 265
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
|
||||
|
|
|
@ -446,5 +446,6 @@
|
|||
#define IMX7D_MU_ROOT_CLK 433
|
||||
#define IMX7D_SEMA4_HS_ROOT_CLK 434
|
||||
#define IMX7D_PLL_DRAM_TEST_DIV 435
|
||||
#define IMX7D_CLK_END 436
|
||||
#define IMX7D_ADC_ROOT_CLK 436
|
||||
#define IMX7D_CLK_END 437
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
|
||||
|
|
|
@ -194,6 +194,7 @@
|
|||
#define VF610_PLL7_BYPASS 181
|
||||
#define VF610_CLK_SNVS 182
|
||||
#define VF610_CLK_DAP 183
|
||||
#define VF610_CLK_END 184
|
||||
#define VF610_CLK_OCOTP 184
|
||||
#define VF610_CLK_END 185
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
|
||||
|
|
Loading…
Reference in a new issue