cxl: Export library to support IBM XSL
This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a stripped down version of the PSL (Power Service Layer) used in some cards such as the Mellanox CX5. Like the PSL, it implements the CAIA architecture, but has a number of differences, mostly in it's implementation dependent registers. The XSL also uses a special DMA cxl mode, which uses a slightly different init sequence for the CAPP and PHB. Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>zero-colors
Christophe Lombard
Michael Ellerman
parent
218ea31039
commit
3ced8d7300
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@ -948,6 +948,7 @@ enum {
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OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
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OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
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OPAL_PHB_CAPI_MODE_DMA = 4,
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OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
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};
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/* OPAL I2C request */
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@ -11,11 +11,16 @@ config CXL_AFU_DRIVER_OPS
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bool
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default n
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config CXL_LIB
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bool
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default n
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config CXL
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tristate "Support for IBM Coherent Accelerators (CXL)"
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depends on PPC_POWERNV && PCI_MSI && EEH
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select CXL_BASE
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select CXL_AFU_DRIVER_OPS
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select CXL_LIB
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default m
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help
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Select this option to enable driver support for IBM Coherent
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@ -3,7 +3,7 @@ ccflags-$(CONFIG_PPC_WERROR) += -Werror
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cxl-y += main.o file.o irq.o fault.o native.o
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cxl-y += context.o sysfs.o pci.o trace.o
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cxl-y += vphb.o phb.o api.o
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cxl-y += vphb.o phb.o api.o cxllib.o
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cxl-$(CONFIG_PPC_PSERIES) += flash.o guest.o of.o hcalls.o
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cxl-$(CONFIG_DEBUG_FS) += debugfs.o
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obj-$(CONFIG_CXL) += cxl.o
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@ -1010,6 +1010,7 @@ static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct den
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void cxl_handle_fault(struct work_struct *work);
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void cxl_prefault(struct cxl_context *ctx, u64 wed);
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int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
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struct cxl *get_cxl_adapter(int num);
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int cxl_alloc_sst(struct cxl_context *ctx);
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@ -1061,6 +1062,11 @@ int cxl_afu_slbia(struct cxl_afu *afu);
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int cxl_data_cache_flush(struct cxl *adapter);
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int cxl_afu_disable(struct cxl_afu *afu);
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int cxl_psl_purge(struct cxl_afu *afu);
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int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
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u32 *phb_index, u64 *capp_unit_id);
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int cxl_slot_is_switched(struct pci_dev *dev);
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int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg);
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u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
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void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
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void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
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@ -0,0 +1,246 @@
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/*
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* Copyright 2017 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/hugetlb.h>
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#include <linux/sched/mm.h>
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#include <asm/pnv-pci.h>
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#include <misc/cxllib.h>
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#include "cxl.h"
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#define CXL_INVALID_DRA ~0ull
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#define CXL_DUMMY_READ_SIZE 128
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#define CXL_DUMMY_READ_ALIGN 8
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#define CXL_CAPI_WINDOW_START 0x2000000000000ull
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#define CXL_CAPI_WINDOW_LOG_SIZE 48
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#define CXL_XSL_CONFIG_CURRENT_VERSION CXL_XSL_CONFIG_VERSION1
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bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags)
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{
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int rc;
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u32 phb_index;
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u64 chip_id, capp_unit_id;
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/* No flags currently supported */
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if (flags)
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return false;
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if (!cpu_has_feature(CPU_FTR_HVMODE))
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return false;
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if (!cxl_is_power9())
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return false;
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if (cxl_slot_is_switched(dev))
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return false;
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/* on p9, some pci slots are not connected to a CAPP unit */
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rc = cxl_calc_capp_routing(dev, &chip_id, &phb_index, &capp_unit_id);
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if (rc)
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return false;
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return true;
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}
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EXPORT_SYMBOL_GPL(cxllib_slot_is_supported);
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static DEFINE_MUTEX(dra_mutex);
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static u64 dummy_read_addr = CXL_INVALID_DRA;
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static int allocate_dummy_read_buf(void)
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{
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u64 buf, vaddr;
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size_t buf_size;
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/*
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* Dummy read buffer is 128-byte long, aligned on a
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* 256-byte boundary and we need the physical address.
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*/
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buf_size = CXL_DUMMY_READ_SIZE + (1ull << CXL_DUMMY_READ_ALIGN);
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buf = (u64) kzalloc(buf_size, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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vaddr = (buf + (1ull << CXL_DUMMY_READ_ALIGN) - 1) &
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(~0ull << CXL_DUMMY_READ_ALIGN);
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WARN((vaddr + CXL_DUMMY_READ_SIZE) > (buf + buf_size),
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"Dummy read buffer alignment issue");
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dummy_read_addr = virt_to_phys((void *) vaddr);
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return 0;
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}
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int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg)
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{
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int rc;
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u32 phb_index;
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u64 chip_id, capp_unit_id;
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if (!cpu_has_feature(CPU_FTR_HVMODE))
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return -EINVAL;
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mutex_lock(&dra_mutex);
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if (dummy_read_addr == CXL_INVALID_DRA) {
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rc = allocate_dummy_read_buf();
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if (rc) {
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mutex_unlock(&dra_mutex);
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return rc;
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}
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}
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mutex_unlock(&dra_mutex);
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rc = cxl_calc_capp_routing(dev, &chip_id, &phb_index, &capp_unit_id);
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if (rc)
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return rc;
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rc = cxl_get_xsl9_dsnctl(capp_unit_id, &cfg->dsnctl);
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if (rc)
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return rc;
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if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
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/* workaround for DD1 - nbwind = capiind */
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cfg->dsnctl |= ((u64)0x02 << (63-47));
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}
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cfg->version = CXL_XSL_CONFIG_CURRENT_VERSION;
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cfg->log_bar_size = CXL_CAPI_WINDOW_LOG_SIZE;
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cfg->bar_addr = CXL_CAPI_WINDOW_START;
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cfg->dra = dummy_read_addr;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cxllib_get_xsl_config);
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int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
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unsigned long flags)
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{
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int rc = 0;
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if (!cpu_has_feature(CPU_FTR_HVMODE))
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return -EINVAL;
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switch (mode) {
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case CXL_MODE_PCI:
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/*
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* We currently don't support going back to PCI mode
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* However, we'll turn the invalidations off, so that
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* the firmware doesn't have to ack them and can do
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* things like reset, etc.. with no worries.
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* So always return EPERM (can't go back to PCI) or
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* EBUSY if we couldn't even turn off snooping
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*/
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rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_OFF);
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if (rc)
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rc = -EBUSY;
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else
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rc = -EPERM;
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break;
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case CXL_MODE_CXL:
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/* DMA only supported on TVT1 for the time being */
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if (flags != CXL_MODE_DMA_TVT1)
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return -EINVAL;
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rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_DMA_TVT1);
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if (rc)
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return rc;
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rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON);
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break;
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default:
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rc = -EINVAL;
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}
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return rc;
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}
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EXPORT_SYMBOL_GPL(cxllib_switch_phb_mode);
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/*
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* When switching the PHB to capi mode, the TVT#1 entry for
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* the Partitionable Endpoint is set in bypass mode, like
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* in PCI mode.
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* Configure the device dma to use TVT#1, which is done
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* by calling dma_set_mask() with a mask large enough.
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*/
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int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags)
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{
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int rc;
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if (flags)
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return -EINVAL;
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rc = dma_set_mask(&dev->dev, DMA_BIT_MASK(64));
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return rc;
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}
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EXPORT_SYMBOL_GPL(cxllib_set_device_dma);
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int cxllib_get_PE_attributes(struct task_struct *task,
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unsigned long translation_mode,
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struct cxllib_pe_attributes *attr)
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{
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struct mm_struct *mm = NULL;
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if (translation_mode != CXL_TRANSLATED_MODE &&
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translation_mode != CXL_REAL_MODE)
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return -EINVAL;
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attr->sr = cxl_calculate_sr(false,
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task == NULL,
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translation_mode == CXL_REAL_MODE,
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true);
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attr->lpid = mfspr(SPRN_LPID);
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if (task) {
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mm = get_task_mm(task);
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if (mm == NULL)
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return -EINVAL;
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/*
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* Caller is keeping a reference on mm_users for as long
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* as XSL uses the memory context
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*/
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attr->pid = mm->context.id;
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mmput(mm);
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} else {
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attr->pid = 0;
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}
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attr->tid = 0;
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return 0;
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}
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EXPORT_SYMBOL_GPL(cxllib_get_PE_attributes);
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int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags)
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{
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int rc;
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u64 dar;
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struct vm_area_struct *vma = NULL;
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unsigned long page_size;
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if (mm == NULL)
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return -EFAULT;
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down_read(&mm->mmap_sem);
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for (dar = addr; dar < addr + size; dar += page_size) {
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if (!vma || dar < vma->vm_start || dar > vma->vm_end) {
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vma = find_vma(mm, addr);
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if (!vma) {
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pr_err("Can't find vma for addr %016llx\n", addr);
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rc = -EFAULT;
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goto out;
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}
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/* get the size of the pages allocated */
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page_size = vma_kernel_pagesize(vma);
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}
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rc = cxl_handle_mm_fault(mm, flags, dar);
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if (rc) {
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pr_err("cxl_handle_mm_fault failed %d", rc);
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rc = -EFAULT;
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goto out;
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}
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}
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rc = 0;
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out:
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up_read(&mm->mmap_sem);
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return rc;
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}
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EXPORT_SYMBOL_GPL(cxllib_handle_fault);
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@ -132,18 +132,15 @@ static int cxl_handle_segment_miss(struct cxl_context *ctx,
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return IRQ_HANDLED;
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}
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static void cxl_handle_page_fault(struct cxl_context *ctx,
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struct mm_struct *mm, u64 dsisr, u64 dar)
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int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar)
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{
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unsigned flt = 0;
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int result;
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unsigned long access, flags, inv_flags = 0;
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trace_cxl_pte_miss(ctx, dsisr, dar);
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if ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) {
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pr_devel("copro_handle_mm_fault failed: %#x\n", result);
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return cxl_ack_ae(ctx);
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return result;
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}
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if (!radix_enabled()) {
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@ -155,9 +152,8 @@ static void cxl_handle_page_fault(struct cxl_context *ctx,
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if (dsisr & CXL_PSL_DSISR_An_S)
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access |= _PAGE_WRITE;
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access |= _PAGE_PRIVILEGED;
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if ((!ctx->kernel) || (REGION_ID(dar) == USER_REGION_ID))
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access &= ~_PAGE_PRIVILEGED;
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if (!mm && (REGION_ID(dar) != USER_REGION_ID))
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access |= _PAGE_PRIVILEGED;
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if (dsisr & DSISR_NOHPTE)
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inv_flags |= HPTE_NOHPTE_UPDATE;
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@ -166,8 +162,21 @@ static void cxl_handle_page_fault(struct cxl_context *ctx,
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hash_page_mm(mm, dar, access, 0x300, inv_flags);
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local_irq_restore(flags);
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}
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pr_devel("Page fault successfully handled for pe: %i!\n", ctx->pe);
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cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0);
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return 0;
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}
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static void cxl_handle_page_fault(struct cxl_context *ctx,
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struct mm_struct *mm,
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u64 dsisr, u64 dar)
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{
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trace_cxl_pte_miss(ctx, dsisr, dar);
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if (cxl_handle_mm_fault(mm, dsisr, dar)) {
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cxl_ack_ae(ctx);
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} else {
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pr_devel("Page fault successfully handled for pe: %i!\n", ctx->pe);
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cxl_ops->ack_irq(ctx, CXL_PSL_TFC_An_R, 0);
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}
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}
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/*
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@ -586,17 +586,17 @@ err:
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#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
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#endif
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static u64 calculate_sr(struct cxl_context *ctx)
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u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9)
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{
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u64 sr = 0;
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set_endian(sr);
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if (ctx->master)
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if (master)
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sr |= CXL_PSL_SR_An_MP;
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if (mfspr(SPRN_LPCR) & LPCR_TC)
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sr |= CXL_PSL_SR_An_TC;
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if (ctx->kernel) {
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if (!ctx->real_mode)
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if (kernel) {
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if (!real_mode)
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sr |= CXL_PSL_SR_An_R;
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sr |= (mfmsr() & MSR_SF) | CXL_PSL_SR_An_HV;
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} else {
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@ -608,7 +608,7 @@ static u64 calculate_sr(struct cxl_context *ctx)
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if (!test_tsk_thread_flag(current, TIF_32BIT))
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sr |= CXL_PSL_SR_An_SF;
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}
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if (cxl_is_power9()) {
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if (p9) {
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if (radix_enabled())
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sr |= CXL_PSL_SR_An_XLAT_ror;
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else
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@ -617,6 +617,12 @@ static u64 calculate_sr(struct cxl_context *ctx)
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return sr;
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}
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static u64 calculate_sr(struct cxl_context *ctx)
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{
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return cxl_calculate_sr(ctx->master, ctx->kernel, ctx->real_mode,
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cxl_is_power9());
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}
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static void update_ivtes_directed(struct cxl_context *ctx)
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{
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bool need_update = (ctx->status == STARTED);
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@ -375,7 +375,7 @@ static u64 get_capp_unit_id(struct device_node *np, u32 phb_index)
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return 0;
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}
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static int calc_capp_routing(struct pci_dev *dev, u64 *chipid,
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int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
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u32 *phb_index, u64 *capp_unit_id)
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{
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int rc;
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@ -408,17 +408,9 @@ static int calc_capp_routing(struct pci_dev *dev, u64 *chipid,
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return 0;
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}
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static int init_implementation_adapter_regs_psl9(struct cxl *adapter, struct pci_dev *dev)
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int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
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{
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u64 xsl_dsnctl, psl_fircntl;
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u64 chipid;
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u32 phb_index;
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u64 capp_unit_id;
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int rc;
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|
||||
rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
u64 xsl_dsnctl;
|
||||
|
||||
/*
|
||||
* CAPI Identifier bits [0:7]
|
||||
|
|
@ -454,6 +446,27 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter, struct pci
|
|||
xsl_dsnctl |= ((u64)0x04 << (63-55));
|
||||
}
|
||||
|
||||
*reg = xsl_dsnctl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
|
||||
struct pci_dev *dev)
|
||||
{
|
||||
u64 xsl_dsnctl, psl_fircntl;
|
||||
u64 chipid;
|
||||
u32 phb_index;
|
||||
u64 capp_unit_id;
|
||||
int rc;
|
||||
|
||||
rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
cxl_p1_write(adapter, CXL_XSL9_DSNCTL, xsl_dsnctl);
|
||||
|
||||
/* Set fir_cntl to recommended value for production env */
|
||||
|
|
@ -505,7 +518,7 @@ static int init_implementation_adapter_regs_psl8(struct cxl *adapter, struct pci
|
|||
u64 capp_unit_id;
|
||||
int rc;
|
||||
|
||||
rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
|
||||
rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
|
|
@ -538,7 +551,7 @@ static int init_implementation_adapter_regs_xsl(struct cxl *adapter, struct pci_
|
|||
u64 capp_unit_id;
|
||||
int rc;
|
||||
|
||||
rc = calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
|
||||
rc = cxl_calc_capp_routing(dev, &chipid, &phb_index, &capp_unit_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
|
|
@ -1897,7 +1910,7 @@ static void cxl_pci_remove_adapter(struct cxl *adapter)
|
|||
|
||||
#define CXL_MAX_PCIEX_PARENT 2
|
||||
|
||||
static int cxl_slot_is_switched(struct pci_dev *dev)
|
||||
int cxl_slot_is_switched(struct pci_dev *dev)
|
||||
{
|
||||
struct device_node *np;
|
||||
int depth = 0;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* Copyright 2017 IBM Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version
|
||||
* 2 of the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _MISC_CXLLIB_H
|
||||
#define _MISC_CXLLIB_H
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <asm/reg.h>
|
||||
|
||||
/*
|
||||
* cxl driver exports a in-kernel 'library' API which can be called by
|
||||
* other drivers to help interacting with an IBM XSL.
|
||||
*/
|
||||
|
||||
/*
|
||||
* tells whether capi is supported on the PCIe slot where the
|
||||
* device is seated
|
||||
*
|
||||
* Input:
|
||||
* dev: device whose slot needs to be checked
|
||||
* flags: 0 for the time being
|
||||
*/
|
||||
bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags);
|
||||
|
||||
|
||||
/*
|
||||
* Returns the configuration parameters to be used by the XSL or device
|
||||
*
|
||||
* Input:
|
||||
* dev: device, used to find PHB
|
||||
* Output:
|
||||
* struct cxllib_xsl_config:
|
||||
* version
|
||||
* capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF
|
||||
* capi BAR size
|
||||
* data send control (XSL_DSNCTL)
|
||||
* dummy read address (XSL_DRA)
|
||||
*/
|
||||
#define CXL_XSL_CONFIG_VERSION1 1
|
||||
struct cxllib_xsl_config {
|
||||
u32 version; /* format version for register encoding */
|
||||
u32 log_bar_size;/* log size of the capi_window */
|
||||
u64 bar_addr; /* address of the start of capi window */
|
||||
u64 dsnctl; /* matches definition of XSL_DSNCTL */
|
||||
u64 dra; /* real address that can be used for dummy read */
|
||||
};
|
||||
|
||||
int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg);
|
||||
|
||||
|
||||
/*
|
||||
* Activate capi for the pci host bridge associated with the device.
|
||||
* Can be extended to deactivate once we know how to do it.
|
||||
* Device must be ready to accept messages from the CAPP unit and
|
||||
* respond accordingly (TLB invalidates, ...)
|
||||
*
|
||||
* PHB is switched to capi mode through calls to skiboot.
|
||||
* CAPP snooping is activated
|
||||
*
|
||||
* Input:
|
||||
* dev: device whose PHB should switch mode
|
||||
* mode: mode to switch to i.e. CAPI or PCI
|
||||
* flags: options related to the mode
|
||||
*/
|
||||
enum cxllib_mode {
|
||||
CXL_MODE_CXL,
|
||||
CXL_MODE_PCI,
|
||||
};
|
||||
|
||||
#define CXL_MODE_NO_DMA 0
|
||||
#define CXL_MODE_DMA_TVT0 1
|
||||
#define CXL_MODE_DMA_TVT1 2
|
||||
|
||||
int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
|
||||
unsigned long flags);
|
||||
|
||||
|
||||
/*
|
||||
* Set the device for capi DMA.
|
||||
* Define its dma_ops and dma offset so that allocations will be using TVT#1
|
||||
*
|
||||
* Input:
|
||||
* dev: device to set
|
||||
* flags: options. CXL_MODE_DMA_TVT1 should be used
|
||||
*/
|
||||
int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags);
|
||||
|
||||
|
||||
/*
|
||||
* Get the Process Element structure for the given thread
|
||||
*
|
||||
* Input:
|
||||
* task: task_struct for the context of the translation
|
||||
* translation_mode: whether addresses should be translated
|
||||
* Output:
|
||||
* attr: attributes to fill up the Process Element structure from CAIA
|
||||
*/
|
||||
struct cxllib_pe_attributes {
|
||||
u64 sr;
|
||||
u32 lpid;
|
||||
u32 tid;
|
||||
u32 pid;
|
||||
};
|
||||
#define CXL_TRANSLATED_MODE 0
|
||||
#define CXL_REAL_MODE 1
|
||||
|
||||
int cxllib_get_PE_attributes(struct task_struct *task,
|
||||
unsigned long translation_mode, struct cxllib_pe_attributes *attr);
|
||||
|
||||
|
||||
/*
|
||||
* Handle memory fault.
|
||||
* Fault in all the pages of the specified buffer for the permissions
|
||||
* provided in ‘flags’
|
||||
*
|
||||
* Shouldn't be called from interrupt context
|
||||
*
|
||||
* Input:
|
||||
* mm: struct mm for the thread faulting the pages
|
||||
* addr: base address of the buffer to page in
|
||||
* size: size of the buffer to page in
|
||||
* flags: permission requested (DSISR_ISSTORE...)
|
||||
*/
|
||||
int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags);
|
||||
|
||||
|
||||
#endif /* _MISC_CXLLIB_H */
|
||||
Loading…
Reference in New Issue