Some Integrator patches that matured for v3.14:
- Use PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR. - Support cascaded interrupts on the SIC. - Complete clock implementation for the IM-PD1. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJSxyvwAAoJEEEQszewGV1zObQQAI7bN0/vmtZkoBbIeoXTAolZ KTEqf+Gdtlny4AvW4PUeutDRr4zvFHKYo5uBbr9bQFl4S89ke29nLXhyrvJbAWJs tujyX0mWb38fosEGeVo3YGbDIw9+O3CMRM+zaHyt/yzcHANnPeecpt3dFNheaTKs W7Axw5YFszpfxs5xQYMrrudbXd6TbsZWSn1pJpNlPvoo8b0HV72ARZNDAM2NO2rY rOSUzl8MKb0tAW7Nj4D8vLqAtYkjA7lX6sdXQBbqpUyTINR5/35ifW/K74q1miMS 3T5ECbwrW9CHSW2jrTt28knafasAsJKCMdJ9SXu7uzOZogglTuBSw52MIhP2QvHS mxOXBHkCazCMum4WndLe1ygSigQZR2SAufmjzESsE82RBF2UmkgqR34aaxag9x/X avxUM/3Opgosa12AD8buSP5NfYqMjvqXzwdNs6YbC1UPqRYIgn9FcJ6cFzkVXoKi GWgz6Ko6MiR9HVDBqw8uHrIBKuaa3oZ5+jt0x54ZuI3tOxV1wUxR3AcgWQsF2tSN nPg8GTvZNiEfo6fWSIx7V2H/txFfAj1Z3JG6tFQTfLtE5G7MssxyNitoxZsIeWuB x1+tnsOQRpBlkUb92LS37ndLJoFfknbCgFUAIgMozntfCRQi/6REWAKGDo0fTOmG +uN+Q6JMFj62jZ6dgumd =cCZc -----END PGP SIGNATURE----- Merge tag 'integrator-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers From Linus Walleij: Some Integrator patches that matured for v3.14: - Use PATCH_PHYS_TO_VIRT and AUTO_ZRELADDR. - Support cascaded interrupts on the SIC. - Complete clock implementation for the IM-PD1. * tag 'integrator-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: clk: versatile: fixup IM-PD1 clock implementation clk: versatile: pass a name to ICST clock provider ARM: integrator: pass parent IRQ to the SIC irqchip: versatile FPGA: support cascaded interrupts from DT ARM: integrator: Default enable ARM_PATCH_PHYS_VIRT, AUTO_ZRELADDR Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
commit
3d7e0207ce
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@ -29,3 +29,8 @@ pic: pic@14000000 {
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clear-mask = <0xffffffff>;
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valid-mask = <0x003fffff>;
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};
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Optional properties:
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- interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
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output is simply connected to the input of another IRQ controller,
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then the parent IRQ shall be specified in this property.
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@ -313,6 +313,8 @@ config ARCH_INTEGRATOR
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bool "ARM Ltd. Integrator family"
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select ARCH_HAS_CPUFREQ
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select ARM_AMBA
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select ARM_PATCH_PHYS_VIRT
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select AUTO_ZRELADDR
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select COMMON_CLK
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select COMMON_CLK_VERSATILE
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select GENERIC_CLOCKEVENTS
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@ -47,8 +47,11 @@
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valid-mask = <0x00000007>;
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};
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/* The SIC is cascaded off IRQ 26 on the PIC */
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sic: sic@ca000000 {
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compatible = "arm,versatile-fpga-irq";
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interrupt-parent = <&pic>;
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interrupts = <26>;
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xca000000 0x100>;
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@ -119,6 +119,7 @@ static const struct clk_ops icst_ops = {
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struct clk *icst_clk_register(struct device *dev,
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const struct clk_icst_desc *desc,
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const char *name,
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void __iomem *base)
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{
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struct clk *clk;
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@ -130,7 +131,7 @@ struct clk *icst_clk_register(struct device *dev,
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pr_err("could not allocate ICST clock!\n");
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return ERR_PTR(-ENOMEM);
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}
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init.name = "icst";
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init.name = name;
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init.ops = &icst_ops;
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init.flags = CLK_IS_ROOT;
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init.parent_names = NULL;
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@ -15,4 +15,5 @@ struct clk_icst_desc {
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struct clk *icst_clk_register(struct device *dev,
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const struct clk_icst_desc *desc,
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const char *name,
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void __iomem *base);
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@ -1,6 +1,6 @@
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/*
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* Clock driver for the ARM Integrator/IM-PD1 board
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* Copyright (C) 2012 Linus Walleij
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* Copyright (C) 2012-2013 Linus Walleij
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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@ -18,20 +18,28 @@
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#include "clk-icst.h"
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struct impd1_clk {
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struct clk *vcoclk;
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char *vco1name;
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struct clk *vco1clk;
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char *vco2name;
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struct clk *vco2clk;
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struct clk *mmciclk;
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char *uartname;
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struct clk *uartclk;
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struct clk_lookup *clks[3];
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char *spiname;
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struct clk *spiclk;
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char *scname;
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struct clk *scclk;
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struct clk_lookup *clks[6];
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};
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/* One entry for each connected IM-PD1 LM */
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static struct impd1_clk impd1_clks[4];
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/*
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* There are two VCO's on the IM-PD1 but only one is used by the
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* kernel, that is why we are only implementing the control of
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* IMPD1_OSC1 here.
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* There are two VCO's on the IM-PD1
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*/
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static const struct icst_params impd1_vco_params = {
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static const struct icst_params impd1_vco1_params = {
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.ref = 24000000, /* 24 MHz */
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.vco_max = ICST525_VCO_MAX_3V,
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.vco_min = ICST525_VCO_MIN,
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};
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static const struct clk_icst_desc impd1_icst1_desc = {
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.params = &impd1_vco_params,
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.params = &impd1_vco1_params,
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.vco_offset = IMPD1_OSC1,
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.lock_offset = IMPD1_LOCK,
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};
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static const struct icst_params impd1_vco2_params = {
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.ref = 24000000, /* 24 MHz */
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.vco_max = ICST525_VCO_MAX_3V,
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.vco_min = ICST525_VCO_MIN,
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.vd_min = 12,
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.vd_max = 519,
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.rd_min = 3,
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.rd_max = 120,
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.s2div = icst525_s2div,
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.idx2s = icst525_idx2s,
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};
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static const struct clk_icst_desc impd1_icst2_desc = {
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.params = &impd1_vco2_params,
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.vco_offset = IMPD1_OSC2,
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.lock_offset = IMPD1_LOCK,
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};
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/**
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* integrator_impd1_clk_init() - set up the integrator clock tree
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* @base: base address of the logic module (LM)
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@ -66,16 +92,39 @@ void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
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}
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imc = &impd1_clks[id];
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clk = icst_clk_register(NULL, &impd1_icst1_desc, base);
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imc->vcoclk = clk;
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imc->vco1name = kasprintf(GFP_KERNEL, "lm%x-vco1", id);
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clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, base);
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imc->vco1clk = clk;
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imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id);
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/* UART reference clock */
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clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
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14745600);
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/* VCO2 is also called "CLK2" */
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imc->vco2name = kasprintf(GFP_KERNEL, "lm%x-vco2", id);
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clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, base);
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imc->vco2clk = clk;
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/* MMCI uses CLK2 right off */
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imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00700", id);
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/* UART reference clock divides CLK2 by a fixed factor 4 */
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imc->uartname = kasprintf(GFP_KERNEL, "lm%x-uartclk", id);
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clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name,
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CLK_IGNORE_UNUSED, 1, 4);
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imc->uartclk = clk;
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imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00100", id);
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imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00200", id);
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imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00100", id);
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imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00200", id);
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/* SPI PL022 clock divides CLK2 by a fixed factor 64 */
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imc->spiname = kasprintf(GFP_KERNEL, "lm%x-spiclk", id);
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clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name,
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CLK_IGNORE_UNUSED, 1, 64);
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imc->clks[4] = clkdev_alloc(clk, NULL, "lm%x:00300", id);
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/* Smart Card clock divides CLK2 by a fixed factor 4 */
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imc->scname = kasprintf(GFP_KERNEL, "lm%x-scclk", id);
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clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name,
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CLK_IGNORE_UNUSED, 1, 4);
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imc->scclk = clk;
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imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00600", id);
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for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
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clkdev_add(imc->clks[i]);
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for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
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clkdev_drop(imc->clks[i]);
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clk_unregister(imc->spiclk);
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clk_unregister(imc->uartclk);
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clk_unregister(imc->vcoclk);
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clk_unregister(imc->vco2clk);
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clk_unregister(imc->vco1clk);
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kfree(imc->scname);
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kfree(imc->spiname);
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kfree(imc->uartname);
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kfree(imc->vco2name);
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kfree(imc->vco1name);
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}
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@ -78,7 +78,7 @@ void __init integrator_clk_init(bool is_cp)
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clk_register_clkdev(clk, NULL, "sp804");
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/* ICST VCO clock used on the Integrator/CP CLCD */
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clk = icst_clk_register(NULL, &cp_icst_desc,
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clk = icst_clk_register(NULL, &cp_icst_desc, "icst",
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__io_address(INTEGRATOR_HDR_BASE));
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clk_register_clkdev(clk, NULL, "clcd");
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}
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@ -84,9 +84,11 @@ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
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/* ICST VCO clock */
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if (is_pb1176)
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clk = icst_clk_register(NULL, &realview_osc0_desc, sysbase);
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clk = icst_clk_register(NULL, &realview_osc0_desc,
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"osc0", sysbase);
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else
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clk = icst_clk_register(NULL, &realview_osc4_desc, sysbase);
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clk = icst_clk_register(NULL, &realview_osc4_desc,
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"osc4", sysbase);
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clk_register_clkdev(clk, NULL, "dev:clcd");
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clk_register_clkdev(clk, NULL, "issp:clcd");
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@ -9,6 +9,7 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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f->used_irqs++;
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}
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pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
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pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs",
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fpga_irq_id, name, base, f->used_irqs);
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if (parent_irq != -1)
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pr_cont(", parent IRQ: %d\n", parent_irq);
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else
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pr_cont("\n");
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fpga_irq_id++;
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}
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void __iomem *base;
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u32 clear_mask;
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u32 valid_mask;
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int parent_irq;
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if (WARN_ON(!node))
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return -ENODEV;
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if (of_property_read_u32(node, "valid-mask", &valid_mask))
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valid_mask = 0;
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fpga_irq_init(base, node->name, 0, -1, valid_mask, node);
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/* Some chips are cascaded from a parent IRQ */
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parent_irq = irq_of_parse_and_map(node, 0);
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if (!parent_irq)
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parent_irq = -1;
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fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
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writel(clear_mask, base + IRQ_ENABLE_CLEAR);
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writel(clear_mask, base + FIQ_ENABLE_CLEAR);
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