From 0b6fbd68b2c45cfa64fa8478643f0345f9a2c99d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:36 +0300 Subject: [PATCH 01/12] ARM: OMAP4+: clock: remove DEFINE_CLK_OMAP_HSDIVIDER macro This clock type declaration is no longer used as all omap4+ SoC clock data has been moved to DT, thus remove it. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.h | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d428d7c..e29f982ce4dd 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -101,31 +101,6 @@ struct clockdomain; }; \ DEFINE_STRUCT_CLK(_name, _parent_names, _ops); -#define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ - _parent_ptr, _flags, \ - _clksel_reg, _clksel_mask) \ - static const struct clksel _name##_div[] = { \ - { \ - .parent = _parent_ptr, \ - .rates = div31_1to31_rates \ - }, \ - { .parent = NULL }, \ - }; \ - static struct clk _name; \ - static const char *_name##_parent_names[] = { \ - _parent_name, \ - }; \ - static struct clk_hw_omap _name##_hw = { \ - .hw = { \ - .clk = &_name, \ - }, \ - .clksel = _name##_div, \ - .clksel_reg = _clksel_reg, \ - .clksel_mask = _clksel_mask, \ - .ops = &clkhwops_omap4_dpllmx, \ - }; \ - DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); - /* struct clksel_rate.flags possibilities */ #define RATE_IN_242X (1 << 0) #define RATE_IN_243X (1 << 1) From 74b9b62b6046265437dd20562c067ba167bd94a4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:37 +0300 Subject: [PATCH 02/12] ARM: OMAP4+: dpll: remove cpu_is_omap44xx checks These are unnecessary, as the clock code is only used on OMAP4+ platforms through clock registrations. This also allows to eventually migrate the clock type implementation under clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/dpll44xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 52f9438b92f2..b0718911f380 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -15,7 +15,6 @@ #include #include -#include "soc.h" #include "clock.h" #include "clock44xx.h" #include "cm-regbits-44xx.h" @@ -35,7 +34,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) u32 v; u32 mask; - if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!clk || !clk->clksel_reg) return -EINVAL; mask = clk->flags & CLOCK_CLKOUTX2 ? @@ -54,7 +53,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) u32 v; u32 mask; - if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!clk || !clk->clksel_reg) return; mask = clk->flags & CLOCK_CLKOUTX2 ? @@ -72,7 +71,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) u32 v; u32 mask; - if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) + if (!clk || !clk->clksel_reg) return; mask = clk->flags & CLOCK_CLKOUTX2 ? From 44b65e760e39323f4dad70a3080b7b624ed481ca Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:38 +0300 Subject: [PATCH 03/12] ARM: OMAP4+: dpll44xx: remove cm-regbits-44xx.h and clock44xx.h includes Instead, copy the used bitfield definitions to the source file. Done in preparation to migrate the clock implementation under clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/dpll44xx.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index b0718911f380..4613f1e86988 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c @@ -16,8 +16,6 @@ #include #include "clock.h" -#include "clock44xx.h" -#include "cm-regbits-44xx.h" /* * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that @@ -28,6 +26,16 @@ #define OMAP4_DPLL_LP_FINT_MAX 1000000 #define OMAP4_DPLL_LP_FOUT_MAX 100000000 +/* + * Bitfield declarations + */ +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) +#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) + +/* Static rate multiplier for OMAP4 REGM4XEN clocks */ +#define OMAP4430_REGM4XEN_MULT 4 + /* Supported only on OMAP4 */ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) { From 8111e01045c1b3ac6b5d3c2ee3b8dc562efdf3ae Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:39 +0300 Subject: [PATCH 04/12] ARM: OMAP2+: clock: introduce ti_clk_features flags This shall be used to replace the cpu type checks around the clock code. Actual bit values will be introduced in patches later. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 14 ++++++++++++++ arch/arm/mach-omap2/clock.h | 10 ++++++++++ arch/arm/mach-omap2/io.c | 2 ++ 3 files changed, 26 insertions(+) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a66532..7897053ce676 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -46,6 +46,11 @@ u16 cpu_mask; +/* + * Clock features setup. Used instead of CPU type checks. + */ +struct ti_clk_features ti_clk_features; + /* * clkdm_control: if true, then when a clock is enabled in the * hardware, its clockdomain will first be enabled; and when a clock @@ -731,3 +736,12 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, (clk_get_rate(core_ck) / 1000000), (clk_get_rate(mpu_ck) / 1000000)); } + +/** + * ti_clk_init_features - init clock features struct for the SoC + * + * Initializes the clock features struct based on the SoC type. + */ +void __init ti_clk_init_features(void) +{ +} diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index e29f982ce4dd..9b89cc03869e 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -223,6 +223,14 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); extern u16 cpu_mask; +/* + * Clock features setup. Used instead of CPU type checks. + */ +struct ti_clk_features { + u32 flags; +}; +extern struct ti_clk_features ti_clk_features; + extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_dummy; extern const struct clkops clkops_omap2_dflt; @@ -261,4 +269,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); extern void omap_clocks_register(struct omap_clk *oclks, int cnt); + +void __init ti_clk_init_features(void); #endif diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8f559450c876..1fae5c123f79 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -728,6 +728,8 @@ int __init omap_clk_init(void) if (!omap_clk_soc_init) return 0; + ti_clk_init_features(); + ret = of_prcm_init(); if (!ret) ret = omap_clk_soc_init(); From a24886e263ec4b7062c88cfa84577080ea00da94 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:40 +0300 Subject: [PATCH 05/12] ARM: OMAP2+: clock: add fint values to the ti_clk_features struct These are SoC specific and get their init values based on the SoC type. Previously the values were hard coded within the DPLL clock code, but having them inside the clock features avoids runtime cpu_is_X type checks. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 34 ++++++++++++--------------------- arch/arm/mach-omap2/clock.c | 23 ++++++++++++++++++++++ arch/arm/mach-omap2/clock.h | 4 ++++ 3 files changed, 39 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 332af927f4d3..05168c98b3d9 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -44,20 +44,12 @@ #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) -/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ -#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 -#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 -#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 -#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 - /* * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. * From device data manual section 4.3 "DPLL and DLL Specifications". */ #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 -#define OMAP3PLUS_DPLL_FINT_MIN 32000 -#define OMAP3PLUS_DPLL_FINT_MAX 52000000 /* _dpll_test_fint() return codes */ #define DPLL_FINT_UNDERFLOW -1 @@ -87,33 +79,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, u8 n) /* DPLL divider must result in a valid jitter correction val */ fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; - if (cpu_is_omap24xx()) { - /* Should not be called for OMAP2, so warn if it is called */ - WARN(1, "No fint limits available for OMAP2!\n"); - return DPLL_FINT_INVALID; - } else if (cpu_is_omap3430()) { - fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; - fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; - } else if (dd->flags & DPLL_J_TYPE) { + if (dd->flags & DPLL_J_TYPE) { fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; } else { - fint_min = OMAP3PLUS_DPLL_FINT_MIN; - fint_max = OMAP3PLUS_DPLL_FINT_MAX; + fint_min = ti_clk_features.fint_min; + fint_max = ti_clk_features.fint_max; } - if (fint < fint_min) { + if (!fint_min || !fint_max) { + WARN(1, "No fint limits available!\n"); + return DPLL_FINT_INVALID; + } + + if (fint < ti_clk_features.fint_min) { pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", n); dd->max_divider = n; ret = DPLL_FINT_UNDERFLOW; - } else if (fint > fint_max) { + } else if (fint > ti_clk_features.fint_max) { pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", n); dd->min_divider = n; ret = DPLL_FINT_INVALID; - } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && - fint < OMAP3430_DPLL_FINT_BAND2_MIN) { + } else if (fint > ti_clk_features.fint_band1_max && + fint < ti_clk_features.fint_band2_min) { pr_debug("rejecting n=%d due to Fint failure\n", n); ret = DPLL_FINT_INVALID; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7897053ce676..7efe66e3a029 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -51,6 +51,19 @@ u16 cpu_mask; */ struct ti_clk_features ti_clk_features; +/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ +#define OMAP3430_DPLL_FINT_BAND1_MIN 750000 +#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 +#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 +#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 + +/* + * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. + * From device data manual section 4.3 "DPLL and DLL Specifications". + */ +#define OMAP3PLUS_DPLL_FINT_MIN 32000 +#define OMAP3PLUS_DPLL_FINT_MAX 52000000 + /* * clkdm_control: if true, then when a clock is enabled in the * hardware, its clockdomain will first be enabled; and when a clock @@ -744,4 +757,14 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, */ void __init ti_clk_init_features(void) { + /* Fint setup for DPLLs */ + if (cpu_is_omap3430()) { + ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; + ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; + ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; + ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; + } else { + ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; + ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; + } } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 9b89cc03869e..02aa2e3ac036 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -228,6 +228,10 @@ extern u16 cpu_mask; */ struct ti_clk_features { u32 flags; + long fint_min; + long fint_max; + long fint_band1_max; + long fint_band2_min; }; extern struct ti_clk_features ti_clk_features; From 5f84aeb6a194ed127d1beb61738577c15a60172b Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:41 +0300 Subject: [PATCH 06/12] ARM: OMAP2+: clock/dpll: add private API for checking if DPLL is in bypass Currently, same functionality is copy pasted in two locations. Instead, add a private API for this and get rid of some duplicated code. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 60 ++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 28 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 05168c98b3d9..098e0893a6a6 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -175,6 +175,33 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, return r; } +/** + * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not + * @v: bitfield value of the DPLL enable + * + * Checks given DPLL enable bitfield to see whether the DPLL is in bypass + * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise. + */ +static int _omap2_dpll_is_in_bypass(u32 v) +{ + if (cpu_is_omap24xx()) { + if (v == OMAP2XXX_EN_DPLL_LPBYPASS || + v == OMAP2XXX_EN_DPLL_FRBYPASS) + return 1; + } else if (cpu_is_omap34xx()) { + if (v == OMAP3XXX_EN_DPLL_LPBYPASS || + v == OMAP3XXX_EN_DPLL_FRBYPASS) + return 1; + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { + if (v == OMAP4XXX_EN_DPLL_LPBYPASS || + v == OMAP4XXX_EN_DPLL_FRBYPASS || + v == OMAP4XXX_EN_DPLL_MNBYPASS) + return 1; + } + + return 0; +} + /* Public functions */ u8 omap2_init_dpll_parent(struct clk_hw *hw) { @@ -191,20 +218,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) v >>= __ffs(dd->enable_mask); /* Reparent the struct clk in case the dpll is in bypass */ - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return 1; - } + if (_omap2_dpll_is_in_bypass(v)) + return 1; + return 0; } @@ -237,20 +253,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return __clk_get_rate(dd->clk_bypass); - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return __clk_get_rate(dd->clk_bypass); - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) - return __clk_get_rate(dd->clk_bypass); - } + if (_omap2_dpll_is_in_bypass(v)) + return __clk_get_rate(dd->clk_bypass); v = omap2_clk_readl(clk, dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; From 512d91cbd990c67df16d0a7b3ff5d35055ac6b39 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:42 +0300 Subject: [PATCH 07/12] ARM: OMAP2+: clock/dpll: convert bypass check to use clk_features OMAP2 DPLL code for checking whether DPLL is in bypass mode now uses clk_features data provided during boot. This avoids the need to use cpu_is_X type checks runtime, and allows us to eventually move the clock code under the clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 25 +++++++++++++------------ arch/arm/mach-omap2/clock.c | 17 +++++++++++++++++ arch/arm/mach-omap2/clock.h | 1 + 3 files changed, 31 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 098e0893a6a6..49333d055f54 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -184,18 +184,19 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, */ static int _omap2_dpll_is_in_bypass(u32 v) { - if (cpu_is_omap24xx()) { - if (v == OMAP2XXX_EN_DPLL_LPBYPASS || - v == OMAP2XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (cpu_is_omap34xx()) { - if (v == OMAP3XXX_EN_DPLL_LPBYPASS || - v == OMAP3XXX_EN_DPLL_FRBYPASS) - return 1; - } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { - if (v == OMAP4XXX_EN_DPLL_LPBYPASS || - v == OMAP4XXX_EN_DPLL_FRBYPASS || - v == OMAP4XXX_EN_DPLL_MNBYPASS) + u8 mask, val; + + mask = ti_clk_features.dpll_bypass_vals; + + /* + * Each set bit in the mask corresponds to a bypass value equal + * to the bitshift. Go through each set-bit in the mask and + * compare against the given register value. + */ + while (mask) { + val = __ffs(mask); + mask ^= (1 << val); + if (v == val) return 1; } diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 7efe66e3a029..e4384377d9f8 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -767,4 +767,21 @@ void __init ti_clk_init_features(void) ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; } + + /* Bypass value setup for DPLLs */ + if (cpu_is_omap24xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP2XXX_EN_DPLL_FRBYPASS); + } else if (cpu_is_omap34xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP3XXX_EN_DPLL_FRBYPASS); + } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || + soc_is_omap54xx() || soc_is_dra7xx()) { + ti_clk_features.dpll_bypass_vals |= + (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | + (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | + (1 << OMAP4XXX_EN_DPLL_MNBYPASS); + } } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 02aa2e3ac036..7b2b099c6a83 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -232,6 +232,7 @@ struct ti_clk_features { long fint_max; long fint_band1_max; long fint_band2_min; + u8 dpll_bypass_vals; }; extern struct ti_clk_features ti_clk_features; From 2337c5b58b6e9fd2fb46ab64e7ccbc44dc0ba40a Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:43 +0300 Subject: [PATCH 08/12] ARM: OMAP2+: clock/dpll: add jitter correction behind clk_features Currently DPLL code uses runtime cpu_is_343x checks to see if the DPLL has freqsel fields in its control register or not. Instead, add a new flag to the clk_features.flags and use this during runtime. Allows eventual move of the DPLL code under clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 4 ++++ arch/arm/mach-omap2/clock.h | 3 +++ arch/arm/mach-omap2/dpll3xxx.c | 4 ++-- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index e4384377d9f8..23b5f050c8a9 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -784,4 +784,8 @@ void __init ti_clk_init_features(void) (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); } + + /* Jitter correction only available on OMAP343X */ + if (cpu_is_omap343x()) + ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 7b2b099c6a83..d3ef147b32a1 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -234,6 +234,9 @@ struct ti_clk_features { long fint_band2_min; u8 dpll_bypass_vals; }; + +#define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) + extern struct ti_clk_features ti_clk_features; extern const struct clkops clkops_omap2_dflt_wait; diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37e2257..12ad0f5b15bf 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -310,7 +310,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) * Set jitter correction. Jitter correction applicable for OMAP343X * only since freqsel field is no longer present on other devices. */ - if (cpu_is_omap343x()) { + if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { v = omap2_clk_readl(clk, dd->control_reg); v &= ~dd->freqsel_mask; v |= freqsel << __ffs(dd->freqsel_mask); @@ -512,7 +512,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, return -EINVAL; /* Freqsel is available only on OMAP343X devices */ - if (cpu_is_omap343x()) { + if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); WARN_ON(!freqsel); From 066edb2d57d7db37121b420409c1deb185069c1d Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:44 +0300 Subject: [PATCH 09/12] ARM: OMAP2+: clock/interface: add a clk_features definition for idlest value Helps to get rid of some runtime cpu_is_x checks. This also allows eventual migration of the code under clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clock.c | 18 +++++++++++------- arch/arm/mach-omap2/clock.h | 1 + 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 23b5f050c8a9..5a0cac93d9ec 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -305,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, * 34xx reverses this, just to keep us on our toes * AM35xx uses both, depending on the module. */ - if (cpu_is_omap24xx()) - *idlest_val = OMAP24XX_CM_IDLEST_VAL; - else if (cpu_is_omap34xx()) - *idlest_val = OMAP34XX_CM_IDLEST_VAL; - else - BUG(); - + *idlest_val = ti_clk_features.cm_idlest_val; } /** @@ -788,4 +782,14 @@ void __init ti_clk_init_features(void) /* Jitter correction only available on OMAP343X */ if (cpu_is_omap343x()) ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; + + /* Idlest value for interface clocks. + * 24xx uses 0 to indicate not ready, and 1 to indicate ready. + * 34xx reverses this, just to keep us on our toes + * AM35xx uses both, depending on the module. + */ + if (cpu_is_omap24xx()) + ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; + else if (cpu_is_omap34xx()) + ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; } diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index d3ef147b32a1..0f100dc4e97f 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -233,6 +233,7 @@ struct ti_clk_features { long fint_band1_max; long fint_band2_min; u8 dpll_bypass_vals; + u8 cm_idlest_val; }; #define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) From b166730c4a73354e8adc886a1ee5a6481564bd27 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:45 +0300 Subject: [PATCH 10/12] ARM: OMAP2+: clock/dpll: remove unused header includes from clkt_dpll.c Some of the machine specific header includes are no longer used, so remove these from the source file. This allows migration of the file under clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_dpll.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 49333d055f54..3c34df0f1531 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -21,10 +21,7 @@ #include -#include "soc.h" #include "clock.h" -#include "cm-regbits-24xx.h" -#include "cm-regbits-34xx.h" /* DPLL rate rounding: minimum DPLL multiplier, divider values */ #define DPLL_MIN_MULTIPLIER 2 From 9ac77edacd2e5ab36d7539046889f6746cb44c90 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:46 +0300 Subject: [PATCH 11/12] ARM: OMAP2+: clock/dpll: remove unused header includes from dpll3xxx.c Some of the machine specific header includes are no longer used, so remove these from the source file. This allows migration of the file under clock driver. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/dpll3xxx.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 12ad0f5b15bf..cd5f3a0b97bd 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -28,11 +28,8 @@ #include #include -#include "soc.h" #include "clockdomain.h" #include "clock.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-34xx.h" /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ #define DPLL_AUTOIDLE_DISABLE 0x0 From acd052bb8119dd9117e0af48ff0ac6e56e61b6b4 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 2 Jul 2014 11:47:47 +0300 Subject: [PATCH 12/12] ARM: OMAP2+: clock/interface: remove some headers from clkt_iclk.c file Instead, copy the used constants from the header file to the source file. This allows the code to be migrated under drivers folder where we don't have access to the OMAP specific header files. Signed-off-by: Tero Kristo Reviewed-by: Mike Turquette Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/clkt_iclk.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 333f0a666171..55eb579aeae1 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c @@ -14,11 +14,11 @@ #include #include - #include "clock.h" -#include "clock2xxx.h" -#include "cm2xxx_3xxx.h" -#include "cm-regbits-24xx.h" + +/* Register offsets */ +#define CM_AUTOIDLE 0x30 +#define CM_ICLKEN 0x10 /* Private functions */